A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method

We have developed a capacitive fingerprint sensor chip using low-temperature poly-Si thin film transistors (TFTs). We have obtained good fingerprint images which have sufficient contrast for fingerprint certification. The sensor chip comprises sensor circuits, drive circuits, and a signal processing circuit. The new sensor cell employs only one transistor and one sensor plate within one cell. There is no leakage current to other cells by using a new and unique sensing method. The output of this sensor chip is an analog wave and the designed maximum output level is almost equal to the TFT's threshold voltage, which is 2-3 V for low-temperature poly-Si TFTs. We used a glass substrate and only two metal layers to lower the cost. The size of the trial chip is 30 mm/spl times/20 mm/spl times/1.2 mm and the sensor area is 19.2 mm/spl times/15 mm. The size of the prototype cell is now 60 /spl mu/m/spl times/60 /spl mu/m at 423 dpi, but it will be easy to increase the resolution up to more than 500 dpi. The drive frequency is now 500 kHz and the power consumption is 1.2 mW with a 5-V supply voltage. This new fingerprint sensor is most suitable for mobile use because the sensor chip is low cost and in a thin package with low power consumption.     

High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

This paper examined the feasibility of applying a highly sensitive metal-oxide-semiconductor (MOS) tunneling temperature sensor, which was compatible with current CMOS technology. As the sensor was biased positively at a constant voltage, the gate current increased more than 500 times when the sensor was heated from 20/spl deg/C to 110/spl deg/C. However, when the sensor was biased at a constant-current situation, its gate voltage magnitude changed significantly with substrate temperature, with a sensitivity exceeding -2 V//spl deg/C. The improvement of temperature sensitivity in this paper is one thousand times over the sensitivity of a conventional p-n junction, i.e., namely, about -2 mV//spl deg/C. Regarding a temperature sensor array, this paper proposes a method using gate current gain, rather than absolute gate current, to eliminate the gate current discrepancy among sensors. For constant current operation, a sensitivity exceeding 10 V//spl deg/C can be obtained if the current level is suitable. Finally, this paper demonstrates a real temperature distribution for on-chip detection. With such a high temperature-sensitive sensor, accurate temperature detection can be incorporated into common CMOS circuits.     

A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor

This paper describes a large-format 4-Mpixel (2352/spl times/1728) sensor with on-chip parallel 10-b analog-to-digital converters (ADCs). The chip size is 20/spl times/20 mm with a 7-/spl mu/m pixel pitch. At a 66-MHz master clock rate and 3.3-V operating voltage, it achieves a high frame rate of 240 frames/s delivering 9.75 Gb/s of data with power dissipation of less than 700 mW. The principal architectural features of the sensor are discussed along with the results of sensor characterization.     

A time-to-digital-converter-based CMOS smart temperature sensor

A time-to-digital-converter-based CMOS smart temperature sensor without a voltage/current analog-to-digital converter (ADC) or bandgap reference is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on voltage/current ADCs for digital output code conversion. For the purpose of cost reduction and power savings, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter is utilized to convert the pulse into a corresponding digital code. The test chips have an extremely small area of 0.175 mm/sup 2/ and were fabricated in the TSMC CMOS 0.35-/spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.7/spl sim/+0.9/spl deg/C after two point calibration, but without any curvature correction or dynamic offset cancellation. The effective resolution is better than 0.16/spl deg/C, and the power consumption is under 10 /spl mu/W at a sample rate of 2 samples/s.     

A chopped Hall sensor with small jitter and programmable "True Power-on" function

A chopped Hall sensor for camshaft applications is presented which provides a programmable "True Power-on" switching level effective after the power-up phase. The proposed chopping technique and self-compensation methods for temperature drift and technology spread provide a correct output state immediately after power-on even at zero speed of the target wheel. The circuits improve the magnetic offsets from 5 to 10 mT to below 200 /spl mu/T in a bandwidth of 30 kHz and stabilize the spread of the magnetic switching points from 20% to <2% in a temperature range from -40/spl deg/C to 175/spl deg/C. The novel combination of chopping and enhanced digital self-calibration algorithm adjusts the magnetic switching point and improves phase accuracy to <0.5/spl deg/, independent of air gap variations between sensor and wheel. An end-of-line calibration for the customer is implemented using surface micromachined cavity fuses which offer a reliable function higher than 195/spl deg/C.     

On the development of a multifunction millimeter-wave sensor for displacement sensing and low-velocity measurement

A new multifunction millimeter-wave sensor operating at 35.6 GHz has been developed and demonstrated for measurement of displacement and low velocity. The sensor was realized using microwave integrated circuits and monolithic microwave integrated circuits. Measured displacement results show unprecedented resolution of only 10 /spl mu/m, which is approximately equivalent to /spl lambda//sub 0//840 in terms of free-space wavelength /spl lambda//sub 0/, and maximum error of only 27 /spl mu/m. A polynomial curve-fitting method was also developed for correcting the error. Results indicate that multiple reflections dominate the displacement measurement error. The sensor was able to measure speed as low as 27.7 mm/s, corresponding to 6.6 Hz in Doppler frequency, with an estimated velocity resolution of 2.7 mm/s. A digital quadrature mixer (DQM) was configured as a phase-detecting processor, employing a quadrature sampling signal-processing technique, to overcome the nonlinear phase response problem of a conventional analog quadrature mixer. The DQM also enables low Doppler frequency to be measured with high resolution. The Doppler frequency was determined by applying linear regression on the phase sampled within only fractions of the period of the Doppler frequency. Short-term stability of the microwave signal source was also considered to predict its effect on measurement accuracy.     

Micro-temperature sensor array with thin-film thermocouples

A micro-temperature sensor array with thin-film thermocouples (TFTCs) is developed. The TFTCs are made with T-type (copper-constantan) thermocouples to measure chip temperature distribution of electronic packaging. The sensor array of 150 nm thickness has 10/spl times/10 junctions within a 9/spl times/9 mm area.     

CMOS integrated silicon pressure sensor

The sensor described includes a four-arm piezoresistance bridge circuit, an amplifier, and a bridge excitation circuit. This circuit is used to stabilize changes in sensitivity due to variations in temperature and supply voltage. The sensor was fabricated using a self-aligned double-poly Si gate p-well CMOS process combined with an electrochemical etch-stop technique using N/SUB 2/H/SUB 4/-H/SUB 2/O anisotropic etchant for the thin-square diaphragm formation. The silicon wafer was electrostatically adhered to a glass plate to minimize thermally induced stress. Less than a /spl plusmn/0.5% sensitivity shift and less than a /spl plusmn/5-mV offset shift were obtained in the 0-70/spl deg/C range, with a 1-V/kg/cm/SUP 2/ pressure sensitivity. By using a novel excitation technique, a sensitivity change of less than /spl plusmn/1.5% under a /spl plusmn/10% supply voltage variation was also achieved.     

A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs

This paper describes a 0.35-/spl mu/m CMOS chopper-stabilized switched-capacitor 2-1 cascade /spl Sigma//spl Delta/ modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (/spl times/0.5,/spl times/1,/spl times/2, and /spl times/4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of -40/spl deg/C to 175/spl deg/C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm/sup 2/ silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution /spl Sigma//spl Delta/ modulators.     

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0/spl deg/, 90/spl deg/, and 270/spl deg/ are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-/spl mu/m CMOS process with five metals. The cell size and the chip size are 0.845 /spl mu/m/sup 2/ and 151.1 mm/sup 2/, respectively.     

A high fill factor and progressive scan PtSi Schottky-barrier IR-CCD image sensor using new wiring technology

A back surface illuminated 130/spl times/130 pixel PtSi Schottky-barrier (SB) IR-CCD image sensor has been developed by using new wiring technology, referred to as CLOSE Wiring, CLOSE Wiring, designed to effectively utilize the space over the SB photodiodes, brings about flexibility in clock line designing, high fill factor, and large charge handling capability in a vertical CCD (VCCD). This image sensor uses a progressive scanned interline-scheme, and has a 64.4% fill factor in a 30 /spl mu/m/spl times/30 /spl mu/m pixel, a 3.9 mm/spl times/3.9 mm image area, and a 5.5 mm/spl times/5.5 mm chip size. The charge handling capability for the 3.3 /spl mu/m wide VCCD achieves 9.8/spl times/10/sup 5/ electrons, The noise equivalent temperature difference obtained was 0.099 K for operation at 120 frames/sec with a 50 mm f/1.3 lens.<>     

New miniature 15-20-GHz continuous-phase/amplitude control MMICs using 0.18-/spl mu/m CMOS technology

The design and performance of two new miniature 360/spl deg/ continuous-phase-control monolithic microwave integrated circuits (MMICs) using the vector sum method are presented. Both are implemented using commercial 0.18-/spl mu/m CMOS process. The first phase shifter demonstrates all continuous phase and an insertion loss of 8 dB with a 37-dB dynamic range from 15 to 20 GHz. The chip size is 0.95 mm /spl times/ 0.76 mm. The second phase shifter can achieve all continuous phase and an insertion loss of 16.2 dB with a 38.8-dB dynamic range at the same frequency range. The chip size is 0.71 mm /spl times/ 0.82 mm. To the best of the authors' knowledge, these circuits are the first demonstration of microwave CMOS phase shifters using the vector sum method with the smallest chip size for all MMIC phase shifters with 360/spl deg/ phase-control range above 5 GHz reported to date.     

A fault-tolerant 256K RAM fabricated with molybdenum-polysilicon technology

Describes a 256K molybdenum-polysilicon (Mo-poly) gate dynamic MOS RAM using a single transistor cell. Circuit technologies, including a capacitive-coupled sense-refresh amplifier and a redundant circuitry, enable the achievement of high performance in combination with Mo-poly technology. Electron-beam direct writing and dry etching technologies are fully utilized to make 1 /spl mu/m accurate patterns. The 256K word/spl times/1 bit device is fabricated on a 5.83 mm/spl times/5.90 mm chip. Cell size is 8.05 /spl mu/m/spl times/8.60 /spl mu/m. The additional 4K spare cells and the associated circuits, in which newly developed electrically programmable elements are used, occupy less than 10 percent of the whole chip area. The measured access time is 160 ns under V/SUB DD/=5 V condition.     

VMOS technology applied to dynamic RAMs

A seven-mask VMOS process has been developed for dynamic RAMs with self-aligned VMOS and planar Al-gate transistors. Using 4 /spl mu/m photolithography, one-transistor cells with a cell size of 150 /spl mu/m/SUP 2/ have been realized. The read signal at the bit line is more than 200 mV. Implementations of a sense amplifier and a word-line driver show that those circuits determine the smallest word and bit line spacing. The paper is concluded by a proposal for a 64K RAM with a chip size of 21 mm/SUP 2/ using 4 /spl mu/m design rules.     

All-solid-state camera for the 525-line television format

A charge-coupled image sensor of the vertical frame transfer type has been fabricated with three-phase three-level polysilicon electrodes. The device has 496 vertically interlaced rows of elements and 475 resolution elements/line. The imaging area, measuring 12.8/spl times/9.6 mm/SUP 2/, corresponds to that of a 1-in vidicon. Defect-free devices have not yet been fabricated, but with an appropriate effort such devices seem feasible. The device is operated in a self-contained camera, measuring 6/spl times/6/spl times/15 cm, containing the countdown circuitry, and implemented with commercially available TTL. The clock line drivers are built with discrete transistors. The camera produces a suitably filtered black-and-white video signal in the standard 525-line television format, which includes the necessary blanking periods and synchronization signals. Large-scale integration (LSI) of these circuits could readily lead to a camera which could be smaller by more than a factor of two.     

Integrated circuits for a 200 Mbit/s fiber-optic link

A set of three bipolar integrated circuits for a new fiber-optic link is described. The link operates at data rates of 5-200 Mb/s NRZ. The optical transmitter and receiver modules are compact and fit into standard 16-pin dual-in-line sockets. The power consumption of the transmitter module is 530 mW and the receiver module dissipates 310 mW. The optical loss budget is 20 dB, which is sufficient for link lengths of up to 5 or 6 km. The circuits have been designed in a 3-/spl mu/m bipolar process. The chip sizes are 2 mm/spl times/1.75 mm each.     

Low-temperature poly-SiGe alloy growth of high gain/speed pin infrared photosensor with gold-induced lateral crystallization (Au-ILC)

The hydrogenated poly-silicon germanium (poly-SiGe:H) epitaxial film has been investigated using gold-induced lateral crystallization (Au-ILC) technology on a-SiGe:H layers at 10-h 350/spl deg/C annealing temperature and 60-sccm hydrogen (H/sub 2/) content. Using this optimal condition, the growth rate of the induced Au was as large as 15.9 /spl mu/m/h. With a low annealing temperature (/spl les/400/spl deg/C) and large growth rate, this novel technology will be noticeably useful for poly-SiGe:H pin IR-sensing fabrication on a conventional precoated indium tin oxide (ITO)-glass substrate. Under a 1-/spl mu/W IR-LED incident light (with peak wave length at 710 nm) and at a 5-V biased voltage, the poly-SiGe:H pin IR sensor developed by the Au-ILC technology, i.e., an Al (anode)/n poly-SiGe:H/i poly-SiGe:H/p poly-SiGe:H/ITO (cathode)/glass-substrate structure allowed for maximum optical gain and response speed. The optical gains and the response speeds were almost 600 and 130%, respectively, better than that of a traditional pin type. Meanwhile, the FWHM of a poly-SiGe:H pin sensor with Au-ILC technology was reduced from 280 to 150 nm. This reveals excellent IR-sensing selectivity. These IR-sensing trials demonstrated again that the proposed Au-ILC technology has very useful application in the field of low cost integrated circuits on optoelectronic applications.     

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.     

High-density CMOS interconnect realized on flexible organic substrate

High-density interconnect integrated circuits (ICs) have been realized on flexible organic substrate with the demonstration of excellent electrical yield and well maintained reliability. Long metal-via chain structures were pre-fabricated with 0.18-/spl mu/m Cu-backend technology on Si-substrate and later transferred onto the organic substrates with wafer-transfer technology. By optimizing the transfer process with thin FR-4 (4 mil /spl ap/0.1 mm), our results demonstrate that both Cu/USG and Cu/low-/spl kappa/ [Black-Diamond (BD)]-based interconnects can be reliably realized over the organic substrate. For via chain structures with via size /spl sim/0.26 /spl mu/m and via number /spl sim/10/sup 4/, the yields were /spl ges/90% and 85% at room temperature and at 100/spl deg/C, respectively. The dielectric breakdown field of the Cu/USG transferred interconnect ICs has been characterized to be /spl ges/5 MV/cm, which is comparable with the results on Si-substrate.     

Static RAMs with microwatt data retention capability

Static RAMs using undoped polysilicon load resistor cells can retain data at less than a nanowatt/bit. This allows large memories to be designed for low-power battery backup applications provided 1) all peripheral circuits can be powered down without disturbing the stored data, and 2) subthreshold leakages of `off' transistors in the memory are at an adequately low level to maintain the stored data during battery backup. Novel circuitry has been developed which assures both conditions without compromising performance. These circuits have been used successfully in 4K and 16K static RAMs, with typical power dissipations of 5 and 12 /spl mu/W, respectively. Data are retained in battery backup over a temperature range in excess of the specified 0-100/spl deg/C, even with rapid skewing of the power supply voltage.