基于2D Mesh拓扑结构的NoC模拟器设计

片上网络模拟器的设计涉及到片上网络的拓扑结构、路由器结构、路由算法、性能分析等诸多方面.从NoC模拟器设计的角度,研究并讨论模拟器所采用的拓扑结构,路由器结构及数据包格式,介绍拓扑结构模拟、IP核模拟、路由模拟,并且用面向对象语言C++实现一个NoC模拟器系统.     

一种二维片上网络路由器的设计实现

片上网络(Network on Chip, NoC)作为解决众核芯片互连的主流方案,其性能很大程度上取决于网络的拓扑结构。而网络拓扑结构的效能受到网络路由器的直接影响。因此,基于特定拓扑结构的路由器设计实现具有非常重要的研究意义。因此将XY路由算法应用于路由器节点中,设计了基于2D Mesh拓扑结构、轮询仲裁机制与虫孔交换流控的片上网络路由器,并使用Modelsim对路由器进行了功能验证。实验结果表明,设计的路由器能满足微片数据的处理,能够正确的收发数据包。     

一种改进的BFT型片上网络拓扑结构

针对片上网络(NoC)资源节点之间通信的局部性,提出改进的蝴蝶型胖树(BFT)拓扑结构XBFT及相应的路由算法.该结构在BFT结构的基础上改变边的连接关系,减少了路由节点数和物理连接链路数,理论分析表明,在64个IP核的NoC中,XBFT较BFT路由器数目减少了14.3％,物理链路数减少了10.7％,XBFT结构比BF...     

支持双拓扑结构的片上网络评估高层仿真平台

为实现高效的NoC（片上网络）性能评估, 缩短系统芯片的开发周期, 针对时钟精确级的NoC仿真方法进行研究, 提出了一种新型的高层次、高效率仿真平台, 与仅支持网格拓扑结构的传统仿真器相比, 其创新地支持了网格和环型双拓扑结构的性能评估, 同时支持虚通道扩展的路由器结构设计, 能快速得到网络的延迟、吞吐率、功耗等性能结果。实验结果表明, 该仿真平台能准确模拟NoC功能行为, 快速获得其仿真性能, 为NoC设计验证提供了高效的方法。     

片上网络拓扑结构

介绍了片上网络（NoC）拓扑结构的相关研究进展。对NoC拓扑结构进行了分类，详细分析了各种网络拓扑的相关特性。从拓扑结构的角度出发，介绍了几种典型的NoC实例，归纳了相关的设计方法。最后，探讨了NoC拓扑结构的发展方向。     

3D NoC网络架构设计

在三维片上网络(3D NoC)设计中,层与层之间通信机制的优劣将影响整个3D NoC系统的性能。为此,在GEMS仿真平台基础上,提出一种低硬件资源消耗、高性能的总线架构,改进路由设计,构造基于总线的3D NoC的路由器。实验结果表明,该架构可提高常见算法的加速比,改善系统的整体性能。     

大规模并行网络模拟系统

为了提高并行网络模拟的真实性、可用性以及运行效率,该文设计并实现了并行分布式互联网模拟使用系统,它可以用网络测量工具获得真实网络数据作为模拟基础,采用优化的拓扑网络划分方法对模拟任务进行划分,采用基于边界路由器的子网间路由配置实现准确的路由模拟,运行脚本的自动生成以及模拟拓扑图的可视化。通过该并行网络模拟使用系统可以实现大规模网络安全事件的模拟,如蠕虫扩散、DDoS攻击等。     

Storus:一个二维片上网络拓扑结构

随着CMOS工艺集成度持续不断提高,单片多处理器正在成为高性能处理器结构的发展趋势,现有的片上总线结构已不足以满足片上系统设计的互连需求,近年来提出了片上网络这一新的互连结构,片上网络需要解决的问题有:选择合适的拓扑结构、路由算法、流控机制等等.文中为片上网络结构提供了一个新的拓扑结构Storus以及路由算法L2,并使用多种负载模式、多种流控机制对Storus与Torus结构进行模拟分析.模拟结果显示,Storus的平均路由延时约比Torus小2%～15%,使用热点负载模拟时,Storus的饱和吞吐量约为Torus结构的1.2～1.5倍.     

一个新颖的模块化NoC路由器设计

片上网络（NoC）作为复杂片上系统的有效解决方案,已经成为研究的热点。互连网络的性能很大程度取决于构建网络的路由器结构。基于时延、吞吐和可靠性等考虑,提出一种基于虫孔交换的模块化设计的路由器结构。该结构采用路径分组,使用更小的交叉开关,同当前设计相比,很大程度上减少了输出端口竞争。且该结构自身具有一定的容错功能。     

NoC节点编码及路由算法的研究

NoC的设计和实现受到芯片的面积、功耗、深亚微米效应的限制.将拓扑结构和节点编码相结合,提出一种基于约翰逊码的二维平面编码.该编码隐含了Torus网络拓扑结构以及网络节点之间的连接关系并且有很好的扩展性,能够简化Torus拓扑结构上路由算法的实现和降低硬件成本.基于此编码和利用X-Y路由的路由确定性特点,提出改进X-Y路由,在中间节点只需要3或5个逻辑运算,降低路由的计算复杂性和硬件成本.最后,进行了节点结构设计.提出的编码不仅用于NoC的路由方面而且在NoC任务映射方面有重要应用.     

用NS2评估片上网络体系结构的性能

随着SoC复杂度的不断提高,总线互连结构面临着越来越严峻的挑战,因此,以网络互连为特点的NoC应运而生。分析了影响NoC性能的几项重要指标,并用网络仿真软件NS2对几种常用拓扑结构的几项性能参数进行了评估,得出了在进行NoC设计时的指导性结论：结合具体的设计,对传输延迟、吞吐量、面积、功耗和可重用性等性能参数进行折衷考虑后选取合适的体系结构。     

支持存储访问的NoC模拟器的设计与实现

随着片上网络的发展,片上多处理器系统通信性能提高的同时,存储器的访问性能将成为片上多处理器系统的性能瓶颈.目前片上网络的研究主要依赖于模拟器,而现有的片上网络模拟器都不能完成对存储器访问的准确模拟.本文设计并实现了一个能对存储器访问进行模拟的模拟器,为存储器性能的研究提供了一个实验平台;论文通过采用大量访问集对该模拟器进行测试,得出了若干条与存储器访问性能优化相关的片上网络设计建议.     

片上网络路由节点优化设计

针对虚输出队列结构的路由节点所构成的片上网络(NoC),提出了一种定制化路由节点中各个虚拟通道缓存大小的方法,以提高片上网络的整体通信性能。在有限的片上缓存资源约束下,分析各个虚输入队列中缓存大小对数据通过片上网络的平均延迟的影响,并在此基础上提出一种缓存资源配置方法,以便将缓存资源分配到片上网络通信瓶颈处,从而在不增加缓存资源开销的情况下提高片上网络的通信性能。最后通过仿真验证了路由节点优化设计对提高片上网络性能的可行性,并同未优化的路由节点构成的片上网络性能进行了比较。     

A networks-on-chip architecture design space exploration – The LIB

Many on-chip network circuit and architecture techniques are incompatible with modern design flows, making them unsuitable for use in systems-on-chip. This paper presents a networks-on-chip (NoC) architecture design space exploration method for multi-processor systems-on-chip architecture. The NoC architecture design space is designed with a Layer-Interactive-Building block (LIB) methodology that is divided into three layers: application layer, link/network layer, and physical layer. The suggested LIB design paradigmatic philosophy provides modular building block structure in both hardware and software and the protocols for their interconnection in the three architecture layers. Using LIB the designer can easily select these building blocks to build application-specific NoCs to meet different application requirements such as media, graphic, software radio and communication network applications. The LIB provides the NoC building blocks, architecture interacting systems-on-chip components, the programming models and application mapping strategies. The LIB can be used as a complementary library and tools for future on-chip interconnection network design.     

A hardwired NoC infrastructure for embedded systems on FPGAs

A hardwired network-on-chip based on a modified Fat Tree (MFT) topology is proposed as a communication infrastructure for future FPGAs. With extremely simple routing, such an infra structure would greatly enhance the ongoing trend of embedded systems implementation using multi-cores on FPGAs. An efficient H-tree based floor plan that naturally follows the MFT construction methodology was developed. Several instances of the proposed NoC were implemented with various inter-routers links progression schemes combined with very simple router architecture and efficient client network interface (CNI). The performance of all these implementations was evaluated using a cycle-accurate simulator for various combinations of NoC sizes and traffic models. Also a new data transfer circuit for transferring data between clients and NoC operating at different (unrelated) clock frequencies has been developed. Allowing data transfer at one data per cycle, the operation of this circuit has been verified using gate-level simulations for several ratios of NoC/client clock frequencies.     

Application-driven dynamic bandwidth allocation for two-layer network-on-chip design

Network-on-Chip (NoC) architecture has been widely used in many multi-core system designs. To improve the communication efficiency and the bandwidth utilization of NoC for various applications, we firstly propose a table-based algorithm for identifying the dominant flows at runtime. Then a two-layer NoC architecture with an application-driven bandwidth allocation scheme is presented, which is capable of identifying heavy-load dataflows and dynamically reconfiguring point-to-point (P2P) connections to optimize the heavy-load traffic. Experimental results reveal that our design (8 × 8 mesh NoC) achieves 28.5% performance improvement and 25.9% power consumption saving compared to the baseline NoC.     

An architectural co-synthesis algorithm for energy-aware Network-on-Chip design

Network-on-Chip (NoC) has been proposed to overcome the complex on-chip communication problem of System-on-Chip (SoC) design in deep sub-micron. A complete NoC design contains exploration on both hardware and software architectures. The hardware architecture includes the selection of Processing Elements (PEs) with multiple types and their topology. The software architecture contains allocating tasks to PEs, scheduling of tasks and their communications. To find the best hardware design for the target tasks, both hardware and software architectures need to be considered simultaneously. Previous works on NoC design have concentrated on solving only one or two design parameters at a time. In this paper, we propose a hardware–software co-synthesis algorithm for a heterogeneous NoC architecture. The design goal is to minimize energy consumption while meeting the real-time requirements commonly seen in embedded applications. The proposed algorithm is based on Simulated-Annealing (SA). To compare the solution quality and efficiency of the proposed algorithm, we also implement the branch-and-bound and iterative algorithm to solve the hardware–software co-synthesis problem of a heterogeneous NoC. With the given synthetic task sets, the experimental results show that the proposed SA-based algorithm achieves near-optimal solution in a reasonable time, while the branch-and-bound algorithm takes a very long time to find the optimal solution, and the iterative algorithm fails to achieve good solution quality. When applying the co-synthesis algorithms to a real-world application with PE library that has little variation in PE performance and energy consumption, the iterative algorithm achieves solution quality comparable to that of the proposed SA-based algorithm.     

An optimised 3D topology for on-chip communications

Increasing system complexity, energy and device reliability, requirement of modular approach, structured layout, effective spatial reuse of resources, scalability and re-programmability have made network-on-chip (NoC) an obvious interconnection design alternative to the ubiquitous bus based on chip communication architecture in system-on-chip. Designing of a topology and its routing scheme plays a vital role in determining performance of any NoC architecture. In recent years, 3D stacked NoC architecture attracts added interest in NoC design as it offers improved performance and shorter global interconnect. In this paper, we have developed a partially, vertically interconnected 3D topology, namely 3D Recursive Network Topology (3D RNT) and prove that the topology has a Hamiltonian connectedness. We have developed deadlock-free routing algorithm for the 3D RNT topology. Also, we compare the performance of the 3D RNT with partially and fully connected 3D mesh topologies (3D PMT and 3D FMT) by conducting suitable experiments. The experiment results show that there is not much deviation in respect of the performance of the 3D RNT on comparing with 3D PMT and 3D FMT even though a number of vertical links are trimmed down to 75%, which is an encouraging outcome as far as design space is concerned.     

Buffer planning for application-specific networks-on-chip design

Networks-on-chip (NoC) is a promising communication architecture for next generation SoC. The size of buffer used in on-chip routers impacts the silicon area and power consumption of NoC dominantly. It is important to plan the total buffer-size and each router buffer-allocation carefully for an efficient NoC design. In this paper, we propose two buffer planning algorithms for application-specific NoC design. More precisely, given the traffic parameters and performance constraints of target application, the proposed algorithms automatically determine minimal buffer budget and assign the buffer depth for each input channel in different routers. The experimental results show that the proposed algorithms can significantly reduce total buffer usage and guarantee the performance requirements. Supported by the National Natural Science Foundation of China (Grant No. 60803018)