微电子器件的抗辐射加固技术

对各类微电子材料的抗辐射特性进行了分析 ,对 Si双极器件和 Si CMOS器件、 Ga As微波功率器件、新兴光电器件—— VCSEL、 LED以及 MEMS的抗辐射加固技术进行了探讨 ,对几种空间单粒子效应 (SEE)进行了研究     

Vacuum microelectronic devices [and prolog]

In this review/tutorial paper, we cover the history, physics, and current status of vacuum microelectronic devices. First we overview the performance requirements of vacuum microelectronic devices necessary for them to replace, or fill voids left by, solid state devices. Next we discuss the physical characteristics of micro-field-emission sources important to device applications. These characteristics include fundamental features, such as current-voltage data and noise, in addition to engineering considerations, such as life expectancy and procedures for tube assembly. We conclude with a review of a wide variety of demonstrated and proposed devices based on vacuum microelectronic principles, including electron guns, microwave tubes, and flat-panel displays     

Reliability of Cu wire bonds in microelectronic packages

In this study the thermo-mechanical response of 25 μm Cu wire bonds in an LQFP-EPad (Low Profile Quad Flat-Exposed Pad) package was investigated by numerical and experimental means. The aim was to develop a methodology for fast evaluation of the packages, with focus on wire bond fatigue, by combining finite element analysis (FEA) and mechanical fatigue testing. The investigations included the following steps: (i) simulation of the warpage induced displacements in the encapsulated LQFP-176-Epad package due to temperature changes, (ii) reproducing the thermally induced stresses in the wire bond loops in an unmolded (non-encapsulated) LQFP package using an accelerated multiaxial mechanical fatigue testing set-up under the displacement amplitudes determined in case (i) and determination of the loading cycles to failure (N_f), (iii) FEA of the experiments performed in (ii) based on the boundary conditions determined in (i) to calculate the states of stress and strain in the wire bonds subjected to multiaxial mechanical cyclic loading. Our investigations confirm that thermal and mechanical cyclic loading results in occurrence of high plastic strains at the heat affected zone (HAZ) above the nail-head, which may lead to fatigue failure of the wire bonds in the packages. The lifetime of wire bonds show a proportional relation between the location and angle of the wire bond to the direction of loading. The calculated accumulated plastic strain in the HAZ was correlated to the experimentally determined N_f values based on the volume weighted averaging (VWA) approached and presented in a lifetime diagram (∆ d - N_f) for reliability assessment of Cu wire bonds. The described accelerated test method could be used as a rapid qualification test for the determination of the lifetimes of wire bonds at different positions on the chip as well as for related improvements of package design.     

Reliability vs component tolerances in microelectronic circuits

It is well known that the reliability of a circuit can be increased by designing it for worst-case conditions so that, even if component characteristics drift, the circuit will still operate satisfactorily. However, it is shown in this paper that extreme worst-case design can lead to increased operating temperature and, therefore, again reduced reliability. A method, illustrated by two practical examples, is indicated to find the compromise in component and circuit design tolerances leading to maximum reliability at any specified time or over any specified time interval.     

Transient IR imaging of light and flexible microelectronic devices

An advanced method for the quality assessment of microelectronic assemblies has been developed by combining IR thermography and several techniques for stimulation by transient temperature fields. The method exploits singularities in materials and interconnections by the observation of perturbations in transient heat flow phenomena. For very light microelectronic systems like chip-on-flex assemblies a method was developed taking advantage of short stimulations by photoflash. Such a method provided possibilities for detecting defects on the level of a single interconnection with a pitch of 80 μm. In addition, a programmable array of thermo-electric converters, prepared for the testing of a large variety of microelectronic assemblies, was also used to perform transient IR imaging for chip-on-flex assemblies.     

应用于微电子的硅基氧化锆薄膜性质研究

用磁控溅射方法在Si(100)衬底上沉积了氧化锆薄膜.研究和比较了退火前和退火后的薄膜晶体结构、表面形貌以及Al/ZrO2/Si电容的金属-绝缘体-半导体性质.700℃氮气退火后的薄膜具有高的介电常数1 8,且在2V时漏电流小于1×10-7A/cm2,显示了良好的电学性质.氧化锆将是一种在未来的微电子器件中大有应用前景的新材料.     

Applications of TEM imaging,analysis and electron holography to III-nitride HEMT devices

This paper reviews some of our recent studies of III-nitride high electron mobility transistor (HEMT) devices using advanced electron microscopy methods. Sample preparation protocols have been developed that can routinely provide thin, electron-transparent specimen regions of uniform thickness extending across entire HEMT devices. The use of focused-ion-beam (FIB) thinning facilitated access to specific device regions, although structural damage and imaging artifacts can result unless suitable precautions are taken during milling to minimize ion-beam damage. The extent of gallium-ion sidewall implantation during FIB milling, and surface damage caused by deposition of Pt protective layers, have been assessed. As-processed device structures have been examined by conventional diffraction contrast imaging as well as high-resolution phase contrast imaging, while nanospectroscopy and nanoscale elemental mapping have been used to measure local variations in chemical composition. Annealing of Ti/Al/Ni/Au ohmic contacts for AlInN/AlN/GaN devices lead to the formation of TiN contact inclusions that are invariably located at mixed-type threading dislocations originating from the underlying GaN layers. Some preliminary observations of device structures after extended periods of operation and after device failure have also been made. The technique of off-axis electron holography has been used to quantify two-dimensional electrostatic fields within cross-sectioned devices with nanometer-scale resolution. Polarization fields of 6.9 MV/cm and a two-dimensional electron gas of ～2.1 × 10¹³/cm² have been measured for an AlInN/AlN/GaN heterostructure. Methods suitable for in situ biasing of HEMT samples during electron holography observations have also been explored.     

A junction characterization for microelectronic devices quality and reliability

With scaling down of devices for higher performance, ageing effects are becoming more important under standard working conditions. They have an important impact on the reliability of microelectronics devices since changes in the devices operating conditions due to lower power consumption are made. This work considers experimental degradations of the emitter–base characteristics in a transistor; the charge transport phenomena are related to structural properties and the evolution of standard operations, which introduce threshold voltage changes related to high injection effects. Both the junction ideality factor and the transient voltage appear as significant and sensitive parameters for quality and reliability characterization or hardness evaluation.A new reliability parameter RF is introduced and related to ageing of devices and to degradation processes.     

Effective decapsulation of copper wire-bonded microelectronic devices for reliability assessment

The wire bonding industry has made a major shift in wire materials from gold to copper, primarily due to cost concerns. Copper wire-bonds are now present in many commercial off-the-shelf (COTS) devices but minimally used in automotive, industrial, or military-grade applications due to lack of detailed understanding about reliability concerns. A thorough study of wire bond reliability includes performing bond shear and pull strength measurements before and after stress testing. This in turn requires a special decapsulation procedure for copper wire-bonded devices because, unlike gold, copper is chemically potent. Many techniques for copper wire-bonded device decapsulation exist and can be categorized into laser-, plasma-, and acid-based processes. This paper reviews some of these techniques and discusses the decapsulation mechanism, which involves decomposition of the epoxy resin. By understanding the decapsulation mechanism and available techniques, a unique decapsulation method was developed. The effectiveness of this method is presented along with scanning electron microscopy (SEM) images of the results, which indicate minimal etching of copper wire bonds. The critical parameters of this technique are also identified, a suitable range of input for each parameter is analyzed theoretically, and a design of experiment (DOE) is conducted to find optimal values for each parameter. Several SEM images are provided to show both the good and bad results from the DOE. An image method for measuring effectiveness of decapsulation is also presented.     

Improved etching method for microelectronic devices with supercritical carbon dioxide

Aqueous etchants used in traditional wet etching for the production of integrated circuits and MEMS devices hinder the processes and pose environmental difficulties. Therefore, we developed an improved dry etching method with HF/Pyridine (7:3) in supercritical carbon dioxide. Etch rates of BPSG, P-TEOS, Thermal SiO₂ and SiN with dry etching method were several times higher than those in wet etching. Etch rates were found to be a function of temperature, HF concentration, and the kind of co-solvents. The presence of alcoholic co-solvents, especially IPA with HF/Pyridine etchant greatly increased the etch rate of BPSG. Etch selectivity could be controlled with the etchant concentration.     

Laser probes for the thermal and thermomechanical characterisation of microelectronic devices

This paper presents a review of some of the recent works that we have done on thermal characterisation of running electronic devices by laser probing. Both the single point probing and the surface imaging methodologies are considered. Besides temperature mapping, laser point probing allows fault detection in integrated circuits. Electronic speckle pattern interferometry and shearography metholologies are presented, and examples of images of running power devices and this relation to the underlying thermomechanical stress are shown.     

Deformation and interfacial sliding in back-end interconnect structures in microelectronic devices

Deformation of interconnect structures at the back-end of microelectronic devices during processing or service can have a pronounced effect on component reliability. Here, we use atomic force microscopy (AFM) to study plastic deformation and interfacial sliding of Cu interconnects on Si. The behavior of both standalone Cu lines and lines embedded in a low-K dielectric (LKD) was studied. Following thermal cycling, changes were observed in the in-plane (IP) Cu line dimensions, as well as the out-of-plane (OOP) step height between Cu and the dielectric in single-layer structures. These were attributed to differential deformation of the Cu/Si and Cu/dielectric material pairs caused by thermal expansion mismatch, accommodated by interfacial creep. These results are discussed in light of previous work on the mechanism of interfacial creep. A simple shear-lag-based model, which may be used to estimate the extent of interfacial sliding, is proposed. Some experimental results on the distortion of Cu lines caused by package-level stresses following thermal cycling are also presented.     

Direct temperature measurement of integrated microelectronic devices by thermally induced leakage currents

We describe an in situ measurement method for the determination of the junction temperature of integrated microelectronic silicon devices. The basic principle of the method is the observation of the junction leakage current of the device. Device operation at sufficient high currents (leading to a high device temperature, typically above 120°C and more) makes the leakage current rise due to device self-heating.This also allows a simple extraction of the thermal resistance of the device. Sample measurements are demonstrated and compared with microfluorescence thermography measurement. For a sample vertical integrated DMOSFET, a very good agreement of both methods is validated.     

Design considerations for acousto-optic devices

The design and fabrication of wide-band bulk acousto-optic modulators (temporal modulation) and beam deflectors (spatial modulation) are described. Optimized device parameters can be obtained systematically for given specifications of the desired modulation bandwidth, throughput efficiency and number of resolvable elements. As the device operating frequency goes beyond a few hundred megahertz, the acoustic transducer response becomes sensitive to the intermediate metal layers between the piezoelectric transducer and the acoustooptic interaction medium. Transducer bandwidth and impedance matching can be optimized using computer modeling programs. Criteria for material selection based on performance requirements and propagation loss are presented. Practical considerations for the fabrication of high performance devices and specific device parameters are discussed.     

Thermal parameters identification of micrometric layers of microelectronic devices by thermoreflectance microscopy

The objective of this paper is the determination of the thermal properties of micrometric layers of electronic devices using a thermoreflectance probe. Unlike classical thermoreflectance methods, the main point of the method presented in this paper is to be able to quantify the heating energy (by Joule effect) and the effective temperature response (by calibration). It is then possible to estimate the thermal conductivity (in W m⁻¹ K⁻¹) instead of the thermal diffusivity (in m² s⁻¹). A semi-analytical thermal 3D-periodic model then enables to identify a few thermal properties of the layers of the device, and in particular the thermal conductivity of the passivation layer. This methodology has been applied to the study of an industrial device containing interconnect test structures made of copper lines on a silicon wafer with a few micrometers BCB (BenzoCycloButene) polymer passivation layer. The BCB thermal conductivity and the metal heat capacity are obtained using this method.     

Reliability of smart power devices

Smart power devices of the last generation are able to integrate a full electronic system, including logic and analog functions and power drivers, in a true single chip solution exploiting the advanced features made available by mixed BCD processes developed for this purpose. The complexity of the ICs and their applications together with the severe stress conditions which these devices can experience in the field makes the reliability assurance of the Smart Power ICs a very challenging task and for this purpose a complete approach is necessary combining an application oriented IC qualification methodology with structural evaluations to test the intrinsic reliability of the basic process elements. In this context the knowledge of the main failure mechanisms is fundamental both for an effective detection in qualification and for an early prevention during IC design.     

Reliability analysis of multiple-state devices

This paper presents two analytical models of special multiple-state devices with repair. The failure rates are constant and the repair rates between failure states are constant, while the repair rate times between failure state and good state are arbitrarily distributed. Laplace transform of the state probabilities and steady-state availability are derived.     

Modeling of interfacial sliding and film crawling in back-end structures of microelectronic devices

The fine-scale of interconnect structures in the back-end of modern microelectronic devices makes them susceptible to unusual, scale-sensitive deformation phenomena during processing or service because of internal stresses induced by thermal expansion mismatch between adjoining materials. During thermo-mechanical cycling associated with processing or service, dimensional changes may occur in Cu interconnect lines embedded in a low-K dielectric (LKD) due to plasticity/creep, strain incompatibilities may arise between Cu and LKD due to diffusionally accommodated interfacial sliding, and Cu lines may crawl or migrate via plastic deformation and interfacial sliding under far-field shear stresses imposed by the package. Although small, these effects can have a pronounced effect on component reliability. This paper presents shear-lag based modeling approaches to simulate out-of-plane (OOP) strain incompatibilities which arise within a single-layer Cu-LKD back-end structure (BES) during back-end processing, and in-plane (IP) deformation and migration of Cu interconnects within the BES after the chip is attached to a flip-chip package. Both models incorporate a previously developed constitutive interfacial sliding law, and help rationalize experimentally observed interfacial strain incompatibilities within Cu-LKD BES.