Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter（ADC） designed in a 0.5-μm CMOS process.Adopting the global and local bias scheme,the number of interconnect signal lines is reduced numerously,and the ADC exhibits the advantages of scalability and portability.Without using linear capacitance,this ADC can be implemented in a standard digital CMOS process;thus,it is suitable for applications in the system on one chip（SoC） design as an analogue IP.Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μA.Adopting the histogram testing method,the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range,respectively.The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB,DNL/INL are-0.005 to ＋0.027 LSB/-0.1 to ＋0.2 LSB,respectively,under a 5 V supply voltage with a digital error correction technique.     

An ll-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

Abstract： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.     

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.     

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm².     

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μ W at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm².     

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

正A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step.     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

An 8 bit 1 MS/s SAR ADC with 7.72-ENOB

This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18 μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5 μ W with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.     

应用于生物医疗的0.6-V 8.3-ENOB 异步时序逐次逼近型模数转换器

A microwatt asynchronous successive approximation register （SAR） analog-to-digital converter （ADC） is presented. The supply voltage of the SAR ADC is decreased to 0.6 V to fit the low voltage and low power require- ments of biomedical systems. The tail capacitor of the DAC array is reused for least significant bit conversion to decrease the total DAC capacitance thus reducing the power. Asynchronous control logic avoids the high frequency clock generator and further reduces the power consumption. The prototype ADC is fabricated with a standard 0.18 μm CMOS technology. Experimental results show that it achieves an ENOB of 8.3 bit at a 300-kS/s sampling rate. Very low power consumption of 3.04 μW is achieved, resulting in a figure of merit of 32 fJ/conv.-step.     

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters： State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.     

A 5 GHz 7.2 dB NF low power direct conversion receiver front-end with balun LNA

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted,and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor.To obtain low l/f noise and high linearity,a current mode passive mixer is preferred and realized.A current mode switching scheme can switch between high and low gain modes,and meanwhile it can not only perform good linearity but save power consumption at low gain mode.The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm~2.It achieves 35 dB conversion gain across 4.9-5.1 GHz,a noise figure of 7.2 dB and an IIP3 of -16.8 dBm,while consuming 28.4 mA from a 1.2 V power supply at high gain mode.Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

一款应用于生物传感器的1.2V-600nW 12bit 2kS/s的增量型模数转换器

This paper presents an ultra-low power incremental ADC for biosensor interface circuits.The ADC consists of a resettable second-order delta–sigma(°/ modulator core and a resettable decimation filter.Several techniques are adopted to minimize its power consumption.A feedforward path is introduced to the modulator core to relax the signal swing and linearity requirement of the integrators.A correlated-double-sampling(CDS)technique is applied to reject the offset and 1/f noise,thereby removing the integrator leakage and relaxing the gain requirement of the OTA.A simple double-tailed inverter-based fully differential OTA using a thick-oxide CMOS is proposed to operate in the subthreshold region to fulfill both an ultra-low power and a large output swing at 1.2 V supply.The signal addition before the comparator in the feedforward architecture is performed in the current domain instead of the voltage domain to minimize the capacitive load to the integrators.The capacitors used in this design are of customized metal–oxide–metal(MOM) type to reach the minimum capacitance set by the k T =C noise limit.Fabricated with a 1P6 M 0.18 m CMOS technology,the presented incremental ADC consumes600 n W at 2 k S/s from a 1.2 V supply,and achieves 68.3 d B signal to noise and distortion ratio(SNDR) at the Nyquist frequency and an FOM of 0.14 p J/conversion step.The core area is 100120 m2.     

采用balun低噪声放大器的5GHz 7.2-dB NF低功耗直接转换接收机前端电路

A 5GHz low power direct conversion receiver radio frequency front-end with balun LNA is presented. A hybrid common gate and common source structure balun LNA is adopted, and the capacitive cross-coupling technique is used to reduce the noise contribution of the common source transistor. To obtain low 1/f noise and high linearity, a current mode passive mixer is preferred and realized. A current mode switching scheme can switch between high and low gain modes, and meanwhile it can not only perform good linearity but save power consumption at low gain mode. The front-end chip is manufactured on a 0.13-μm CMOS process and occupies an active chip area of 1.2 mm². It achieves 35 dB conversion gain across 4.9-5.1 GHz, a noise figure of 7.2 dB and an IIP3 of -16.8 dBm, while consuming 28.4 mA from a 1.2 V power supply at high gain mode. Its conversion gain is 13 dB with an IIP3 of 5.2 dBm and consumes 21.5 mA at low gain mode.     

A 10 bit 200 MS/s pipeline ADC using loading-balanced architecture in 0.18 μm CMOS

A new loading-balanced architecture for high speed and low power consumption pipeline analog-to-digital converter (ADC) is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing technique, capacitor-scaling scheme to reduce the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage, by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system''s point of view, all load capacitors of the shared OTAs are balanced by employing a loading-balanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of 1.2×1.2 mm². The measurement results show a 55.58 dB signal-to-noise-and-distortion ratio (SNDR) and 62.97 dB spurious-free dynamic range (SFDR) with a 25 MHz input operating at a 200 MS/s sampling rate. The proposed ADC consumes 115 mW at 200 MS/s from a 1.8 V supply.     

一种带有混合平均式分布采样电路的低功耗CMOS全折叠型模数转换器

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

A sub-1 V high-precision CMOS bandgap voltage reference

A third-order, sub-1 V bandgap voltage reference design for low-power supply, high-precision applications is presented. This design uses a current-mode compensation technique and temperature-dependent resistor ratio to obtain high-order curvature compensation. The circuit was designed and fabricated by SMIC 0.18 μm CMOS technology. It produces an output reference of 713.6 mV. The temperature coefficient is 3.235 ppm/℃ in the temperature range of -40 to 120 ℃, with a line regulation of 0.199 mV/V when the supply voltage varies from 0.95 to 3 V. The average current consumption of the whole circuit is 49 μA at the supply voltage of 1 V.     

基于干电极的、低功耗的便携式心电传感器接口

This paper describes a low-power portable sensor interface dedicated to sensing and processing electrocardiogram (ECG) signals.Dry electrodes were employed in this ECG sensor,which eliminates the need of conductive gel and avoids complicated and mandatory skin preparation before electrode attachment.This ECG sensor system consists of two ICs,an analog front-end(AFE) and a successive approximation register analog-todigital converter(SAR ADC) containing a relaxation oscillator.This proposed design was fabricated in a 0.18μm 1P6M standard CMOS process.The AFE for extracting the biopotential signals is essential in this ECG sensor. In measurements,the AFE obtains a mid-band gain of 45 dB,a bandwidth from 0.6 to 160 Hz,and a total input referred noise of 2.8μV rms while consuming 1μW from the 1.8 V supply.The noise efficiency factor(NEF) of our design is 3.4.After conditioning,the amplified ECG signal is digitized by a 12-bit SAR ADC with 61.8 dB SNDR and 220 fJ/conversion-step.Finally,a complete ECG sensor interface with three dry copper electrodes is demonstrated in real-word setting,showing successful recordings of a capture ECG waveform.     

一款用于数字电视调谐器的高线性度多频带增益可调信道选择滤波器

This paper presents a channel-select filter that employs an active-RC bi-quad structure for TV-tuner application. A design method to optimize the IIP3 of the bi-quad is developed. Multi-band selection and gain adjustment are implemented using switching resistors in the resistor array and capacitors in the capacitor array. Q-factor degradation is compensated by a tuning segmented resistor. A feed-forward OTA with high gain and low third-order distortion is applied in the bi-quad to maximize linearity performance and minimize area by avoiding extra compensation capacitor use. An RC tuning circuit and DC offset cancellation circuit are designed to overcome the process variation and DC offset, respectively. The experimental results yield an in-band IIP3 of more than 31 dBm at 0 dB gain, a 54 dB gain range with 6 dB gain step, and a continuous frequency tuning range from 0.25 to 4 MHz. The in-band ripple is less than 1.4 dB at high gain mode, while the gain error and frequency tuning error are no more than 3.4% and 5%, respectively. The design, which is fabricated in a 0.18 μm CMOS process, consumes 12.6 mW power at a 1.8 V supply and occupies 1.28 mm2.     

Low power design of a field sequential color LCoS chip

The low power design of a field sequential color （FSC） liquid crystal on silicon （LCoS） chip for near-to-eye application is presented in this paper. Dual power supplies are used in the design, that is, the supply for part of driving circuits is 3.3 V, and the one for the active matrix is 5.0 V. Serial-to-parallel conversion circuits are adopted to lower the pixel clock frequency of the chip. Also, an idle state is inserted into the pixel clock signal to decrease the switching activity factor to further reduce the power consumption. The LCoS chip is fabricated with 0.35 μm CMOS process and its power consumption is only about 300 mW.