Low-voltage constant-gm rail-to-rail CMOS operational amplifier input stage

This paper presents a rail-to-rail constant-g_m operational amplifier input stage. The proposed circuit changes the tail current of the input differential pairs dynamically for a constant-g_m by using dummy input differential pairs. The problem which causes total g_m variation is input pairs and dummy input pairs can not take effect at the same time with the common-mode input voltage changes, because the tail current transistor of the input pairs are in triode region when the input pairs are turned off, the dummy input pairs will enter subthreshold region from cut-off region before the input pairs when common-mode voltage changes. The effect of this problem is more obviously in low supply voltage design. To solve this problem, compensate current sources is added to the tail current transistors of each dummy input differential pairs for lower g_m variation. The g_m of this Op Amp’s input stage varies around ±2%.     

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter

This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 μm CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is ±1 V, and measured input referred RMS noise is 220 μV. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR     

High-performance self-aligned gate AlGaAs/GaAs MODFET voltage comparator

A very high-performance voltage comparator circuit has been demonstrated using self-aligned gate AlGaAs/GaAs modulation-doped FET's (MODFET's)and laser-trimmable CrSi-based thin-film resistors. The MODFET master/slave comparator circuits demonstrated analog input resolutions of < 1 and 2.5 mV at sampling rates of 0.5 and 1 GHz, respectively, at Nyquist analog input rates at room temperature. The MODFET comparators operated to sampling rates greater than 2.5 GHz at Nyquist analog input rates. Static hysteresis of less than 1 mV was observed for some comparators at room temperature. The self-aligned gate MODFET's demonstrated average threshold-voltage offsets for closely spaced FET pairs of 2.53 ± 1.15 mV, and typical static hysteresis levels of < 1 to 3 mV. These MODFET comparators demonstrated the highest analog input resolution at gigahertz sampling frequencies ever reported, including comparators fabricated using AlGaAs/GaAs heterojunction bipolar transistors (HBT's).     

A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA

This paper proposes a circuit to linearize the signal current and improve the distortion characteristics at the input of a current-mode circuit. Input voltage-to-current (V/I) conversion is carried out by a resistor that connects the signal source and the current input terminal of the current-mode circuit. The signal current flowing into the current-mode circuit through this resistor is distorted because of the signal-dependent voltage change at the current input terminal, and it is linearized by injecting a current that is proportional to the signal-dependent voltage change at the current input terminal, into the same current input terminal of the current-mode circuit. A current-mode sample-and-hold amplifier (SHA) that adopts the proposed scheme was fabricated and a 0.35-$mu{hbox {m}}$ CMOS process was used to verify the effectiveness of the scheme. It operated from a 2-V supply voltage in the analog part and a 2.5 V in the digital part with a 100-MHz clock and realized a 77- and a 86-dB spurious-free dynamic range values for 0 and $-$10 dB of full-scale signal current level $(pm hbox{100} mu{hbox {A}})$, respectively, of the 1-MHz signal input. More than a 13-bit equivalent SFDR for $-$14 to $-$4 dB of full-scale input was obtained, proving the effectiveness of the proposed scheme at realizing distortionless signal current processing.      

0.18 /spl mu/m 3-6 GHz CMOS broadband LNA for UWB radio

A 3-6 GHz CMOS broadband low noise amplifier (LNA) for ultra-wideband (UWB) radio is presented. The LNA is fabricated with the 0.18 /spl mu/m 1P6M standard CMOS process. Measurement of the CMOS LNA is performed using an FR-4 PCB test fixture. From 3 to 6 GHz, the broadband LNA exhibits a noise figure of 4.7-6.7 dB, a gain of 13-16 dB, and an input/output return loss higher than 12/10 dB, respectively. The input P/sub 1 dB/ and input IP3 (IIP3) at 4.5 GHz are about -14 and -5 dBm, respectively. The DC supply is 1.8 V.     

High-power 1.3-/spl mu/m InGaAsP-InP amplifiers with tapered gain regions

Tapered structures fabricated in InGaAsP-InP 1.3-/spl mu/m quantum-well material have been evaluated as high-gain high-saturation-power amplifiers. The devices, which had a 1-mm-long ridge-waveguide input gain section followed by a 2-mm-long tapered section, demonstrated an unsaturated gain of 26 dB at 2.0 A and about 30 dB at 2.8 A. Saturated output power at 2.8 A was >750 mW. At 2.0-A drive current and /spl ap/10-mW input power, the relative intensity noise of the amplified signal was /spl les/-160 dB/Hz at frequencies /spl ges/2 GHz.     

A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm² active area, fabricated in 0.35-μm CMOS     

Mixed analog/digital, FIR/IIR realization of a linear-phase lowpassfilter

A 5 kHz linear-phase lowpass filter is implemented in a 2-μm BiCMOS technology as a combination of sigma-delta front-end, a digital shift register, a switched capacitor (SC) summer circuit with 50 input capacitors, and an SC biquad running at a 1 MHz clock. The measured group delay variation in the passband is less than 1 μs and the measured total harmonic distortion (THD) is -80 dB for an input sine wave amplitude of 0.7 V at 1 kHz. The circuit consumes 80 mW from ±5 V supply and measures 8.12 mm² without pads     

A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration

The design of a 600-MS/s 5-bit analog-to-digital (A/D) converter for serial-link receivers has been investigated. The A/D converter uses a closed-loop pipeline architecture. The input capacitance is only 170 fF, making it suitable for interleaving. To maintain low power consumption and increase the sampling rate beyond the amplifier settling limit, the paper proposes a calibration technique that digitally adjusts the reference voltage of each pipeline stage. Differential input swing is 400 mV/sub p-p/ at 1.8-V supply. Measured performance includes 25.6 dB and 19 dB of SNDR for 0.3-GHz and 2.4-GHz input frequencies at 600 MS/s for the calibrated A/D converter. The suggested calibration method improves SNDR by 4.4 dB at 600 MS/s with /spl plusmn/0.35 LSB of DNL and /spl plusmn/0.15 LSB of INL. The 180 /spl times/ 1500 /spl mu/m/sup 2/ chip is fabricated in a 0.18-/spl mu/m standard CMOS technology and consumes 70 mW of power at 600 MS/s.     

A fully monolithic 260-/spl mu/W, 1-GHz subthreshold low noise amplifier

A micro-power complementary metal oxide semiconductor (CMOS) low-noise amplifier (LNA) is presented based on subthreshold MOS operation in the GHz range. The LNA is fabricated in an 0.18-/spl mu/m CMOS process and has a gain of 13.6 dB at 1 GHz while drawing 260 /spl mu/A from a 1-V supply. An unrestrained bias technique, that automatically increases bias currents at high input power levels, is used to raise the input P1dB to -0.2 dBm. The LNA has a measured noise figure of 4.6 dB and an IIP3 of 7.2 dBm.     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

10 Gsample/s optoelectronic A/D converter

A 5 bit, 10 Gsample/s flash A/D converter (ADC) is fabricated for 10 Gbit/s optical receivers. To achieve a 10 Gsample/s rate with wide signal bandwidth, the design focuses on reducing aperture uncertainty, clock skew, and metastability error. The ADC achieves 4.1 effective bits at low input frequencies and 2.8 effective bits at 4.9 GHz input signal at 10 Gsample/s.     

A rail-to-rail amplifier input stage with /spl plusmn/0.35%g/sub m/ fluctuation

A new scheme for achieving rail-to-rail input to an amplifier is introduced. Constant g/sub m/ is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common-mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as common-mode rejection ratio and gain-bandwidth product degradation that exist in many other designs. The circuit was fabricated in 0.5-/spl mu/m process. The resulting differential pair had a constant transconductance that varied by only /spl plusmn/0.35% for rail-to-rail input common-mode levels. The input common-mode range extended well past the supply levels of /spl plusmn/1.5V, resulting in only /spl plusmn/1% fluctuation in g/sub m/ for input common modes from -2 to 2 V.     

An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption

Low power consumption and small chip area (2.09 mm×2.15 mm) are achieved by introducing a new architecture to a subranging A/D converter. In this architecture, both coarse and fine A/D conversions can be accomplished. Consequently, a large number of comparators and processing circuits have been removed from the conventional subranging A/D converter. This architecture has been realized by the introduction of a chopper-type comparator with three input terminals which makes both coarse and fine comparisons by itself. The A/D converter has two 8-b sub/A/D converters which employ this new architecture, and they are pipelined to improve the conversion rate. Good experimental results have been obtained. Both the differential and the integral nonlinearity are less than ±0.5 LSB at a 20-megasample/s sample frequency. The effective resolution at 20-megasample/s sampling frequency is 7.4 b at a 1.97-MHz input frequency and 6.7 b at a 9.79-MHz input frequency. The A/D converter has been fabricated in a 1-μm CMOS technology     

Analysis of N×N passive optical starcoupler based on the normal modes of N input waveguides

An integrated passive N×N optical star coupler on silicon wafer is described. Antiresonant reflecting optical waveguides (ARROWs) are analyzed and utilized as the input and output waveguides of the N×N coupler. Combining the exact solutions of the slab ARROW waveguide with the effective index method, a 5×5 coupler is analyzed. In the slab waveguide analysis, the input waveguides are coupled to their neighbors. The interaction of the waveguides is described in terms of the normal modes of propagation. The resultant field distribution is then diffracted into the free space region which separates the input and output sections. The radiation illuminates the receiving aperture from which the receiving N waveguides branch out, each output element obtaining equal power levels. Different types of loss such as spillover loss and mismatch loss were analyzed and estimated for N=5. A 5×5 star coupler with a transmission efficiency of 56% at a wavelength of 1.3 μm is achievable     

Integrated bipolar master/slave D-flip-flop with multiplexing capability for Gbit/s operation

A versatile integrated bipolar circuit developed for a broadband communication system is described. It consists of a master/slave D-flip-flop with a 2:1 time-division multiplexer at the input and a powerful buffer stage at the output. Despite realisation in a relatively simple bipolar technology, bit rates up to 1.5 Gbit/s (NRZ) were measured.     

A 1.5-V 75-dB dynamic range third-order G/sub m/-C filter integrated in a 0.18-/spl mu/m standard digital CMOS process

A design methodology of a CMOS linear transconductor for low-voltage and low-power filters is proposed in this paper. It is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-/spl mu/m standard digital CMOS process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 /spl mu/W.     

Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode

A family of compact CMOS rail-to-rail input stages with constant-g _m is presented. To attain a constant-g_m over the whole common-mode input range, an electronic zener diode is inserted between the tails of the complementary input pairs. This zener keeps the sum of the gate-source voltages of the input pairs, and therefore the g _m of the rail-to-rail input stage, constant. Two possible implementations of the zener have been realized and inserted in a rail-to-rail input stage. These input stages are implemented in two two-stage compact amplifiers. Both amplifiers have been realized in a 1 μm BiCMOS process. They have a unity-gain frequency of 2-MHz, for a capacitive load of 20 pF     

Compound current conveyor (CCII+ and CCII-)

A CMOS current conveyor configurable as CCII⁺ and/or CCII^- is proposed. The circuit has the advantages of providing two symmetrical outputs, presenting a low input resistance and giving a high output to input resistance ratio. An input resistance of 28 Ω with a zero at 6 MHz in a 0.5 μm implementation with a supply voltage of 3.3 V have been obtained     

A Q-band monolithic balance resistive HEMT mixer usingCPW/slotline balun

A Q-band balanced, resistive high-electron-mobility-transistor (HEMT) mixer has been developed for integration in monolithic millimeter-wave receivers. The mixer consists of two AlGaAs/GaAs HEMTs, a coplanar-waveguide (CPW)-to-slotline local oscillator (LO) balun, and an active IF balun. CPWs are used to eliminate the backside or via-hole process step, which increases the circuit yield and shortens the processing time. The conversion loss of the mixer while downconverting a 42-46-GHz RF to a 2.3-3.2-GHz IF is between 4 and 8 dB using an LO drive of 14 dBm. A 17.5-dBm input two-tone third-order intermodulation intercept point is achieved with an LO drive of 10.5 dBm, while a 5.5-dBm input, 1-dB compression point can be achieved with an LO drive of 14 dBm. This is the first reported monolithic CPW resistive HEMT mixer operating at Q-band frequencies