开关电源控制芯片宏模型的自动生成

开关电源控制苍片宏模型是开关电源CAD中一个重要组成部分。本文讨论了开关电源控制芯片宏模型的自动生成方法，分两类构造了控制芯片的整体拓扑和各功能单元宏模型，并详细介绍了宏模型的生成步骤，实现了自动生成软件，最后给出了测试结果。     

建立高速数字I/O缓冲器宏模型的模糊逻辑方法

如何构造精确有效的数字电路I/O缓冲器宏模型用于系统级的仿真,是高速电路信号完整性分析中的重要问题.本文提出了一种基于模糊逻辑,对数字电路的I/O缓冲器瞬态行为建模的方法.采用一阶Sugeno模糊系统,用平均分割法生成初始模型,再通过BP.最小二乘混合学习算法消除误差.模型可综合成SPICE环境下的子电路,应用十分方便.计算实例表明方法是有效的.     

基于符号分析和统计分析的宏模型自动建立方法

符号分析和统计分析是自动建立宏模型的常用方法．本文综合了这两种方法，提出一种新的宏模型自动建立方法，克服了分别利用以上两种方法建立宏模型的缺陷，使建立的宏模型具有更高的精度本文结出了应用新方法建立宏模型的实例，并与SPICE模拟结果进行了比较，以说明新方法的有效性．     

基于状态机自动生成的SoC硬件接口综合方法

在SoC接口综合方法设计中，由于大多数IP的接口设计和通信协议是不同的，所以必须要发展能结合不同通信协议IP模块的方法。文章提出了一种基于状态机(FSM)自动生成的硬件接口综合方法，其在给定两个子模块的HDL模型的情况下，根据数据传送的逆过程就可以自动生成与其通信的状态机，同时．该方法也给出了一个参数化的缓冲器和数据格式转换．用户可以根据需要选择合适的库。最后，通过一个实例验证了该方法并给出了仿真波形。     

模拟集成电路宏模型计算机辅助自动建立

本文提出一种新的模拟集成电路宏模型计算机辅助自动建立方法，通用性强，宏模型精度高。     

Sigma Delta调制器高效行为级建模

提出一种宏模型和Verilog-A模型相结合的方法对两阶、1位量化的Sigma Delta调制器进行建模.对调制器中的关键模块采用宏模型建模,对功能性模块采用Verilog-A描述.在Cadence环境下,基于华虹NEC 0.25μmCMOS工艺对模块进行设计和仿真,并与实际电路模块仿真结果和仿真时间进行对比,给出两种情况下调制器总体电路的SNR仿真结果.结果显示:这种建模方法既达到了较高的精度,又取得了较快的仿真速度.     

高压LDMOS晶体管宏模型及栅电荷建模方法

针对标准MOSFET的BSIM4模型在高压LDMOS建模及已有LDMOS紧凑模型的不足,提出一种LDMOS宏模型。在本研究中,借助Spectre软件分别对宏模型与BSIM4器件模型进行仿真,并对2种LDMOS器件模型下的CV结果进行对比,验证了宏模型对LDMOS器件模拟的准确性。最后,提出利用栅电荷曲线来进一步修正模型参数的新方法,并通过仿真获得更精确的LDMOS器件模型。该宏模型及栅电荷建模方法对于高压功率集成电路设计及仿真有重要意义。     

垂直腔体面发射激光器等效电路模型在SPICE下的实现

介绍了一个基于速率方程的垂直腔体面发射激光器(VCSEL)的等效电路模型,该模型在电路模拟程序Pspice下得到了实现,其仿真结果与实验数据十分吻合。用C语言编写了一个可以自动生成VCSEL宏模型的网表自动生成器。     

模拟集成电路宏模型计算机辅助自动建立

本文提出一种新的模拟集成电路宏模型计算机辅助自动建立方法,通用性强、宏模型精度高。文中详细描述了建立过程,给出相应的软件流程,并对建立过程中的一些关键算法进行了探讨和创新。最后给出利用新方法建立二级运放宏模型的实例。     

真空三极管的Pspice宏模型的精确化

介绍了应用于Pspice仿真的真空三极管的两种宏模型及其数学模型，并应用Matlab最优化及曲线拟合这种新方法对模型参数进行计算，且使用此模型对应用于中性束诊断系统的大功率负高压脉冲电源中的大功率三极管进行了研究。     

Performance evaluation of some efficient stop-and-wait techniques

The author presents an efficient stop-and-wait ARQ (automatic repeat request) technique for error control in data communication systems. Performance of the proposed stop-and-wait ARQ scheme is derived in terms of throughput efficiency, mean waiting time and buffer occupancy. It is shown that the scheme provides better performance with the respect to previously proposed schemes. In particular it is attractive for error control in data communication systems under high error rate conditions     

A go-back-N protocol for mobile communications

The author describes a go-back-N (GBN) protocol, which is a type of automatic repeat request (ARQ) technique. The protocol has a buffer and memory at the receiver side and offers low implementation complexity and a structure especially suited to mobile communications. The optimization of the protocol parameters is determined through numerical analysis. Performance is evaluated by computer simulation using a channel model suitable for mobile communications. The results show that the proposed ARQ scheme achieves a higher performance than that of other ARQ protocols and that at high error rates its efficiency compares favorably with selective repeat protocols having an infinite buffer     

A selective-repeat-ARQ protocol for parallel channels and itsresequencing analysis

A communications system in which multiple parallel channels are available to carry traffic from a transmitter to a receiver is considered, and an extension of the selective-repeat automatic repeat request (SR-ARQ) protocol that dynamically assigns packets to channels for each (re)transmission is presented. Because of selective retransmission, packets arrive at the receiver out of order and must be stored in a resequencing buffer. A queuing model for the resequencing buffer is constructed. The generating function of the buffer occupancy and the packet-delay distribution are derived, and procedures for simplifying the computation are presented. The dynamic assignment scheme is compared with, and shown to have performance superior to, a static assignment scheme     

Scalable resource management for high‐performance Web servers

Although many research efforts have been devoted to network congestion in the face of an increase in the Internet traffic, there is little recent discussion on performance improvements for endhosts. In this paper, we propose a new architecture, called scalable socket buffer tuning (SSBT), to provide high‐performance and fair service for many TCP connections at Internet endhosts. SSBT has two major features. One is to reduce the number of memory accesses at the sender host by using some new system calls, called Simple Memory‐copy Reduction (SMR) scheme. The other is equation‐based automatic TCP buffer tuning (E‐ATBT), where the sender host estimates ‘expected’ throughput of the TCP connections through a simple mathematical equation, and assigns a send socket buffer to them according to the estimated throughput. If the socket buffer is short, max–min fairness policy is used. We confirm the effectiveness of our proposed algorithm through both simulation technique and an experimental system. From the experimental results, we have found that our SSBT can achieve up to a 30% gain for Web server throughput, and a fair and effective usage of the sender socket buffer can be achieved. Copyright © 2004 John Wiley & Sons, Ltd.     

天线方向图自动测试系统的设计

天线方向图是雷达的一项重要性能指标,方向图的自动测试在雷达性能测试中占有极其重要的位置。介绍了天线方向图测试原理,设计了一种雷达天线方向图自动测试系统。分析了该方向图自动测试系统的电路组成及信号采集与数据处理原理。控制电路由单片机组成,角度录取采用角度-数字转换模块。该系统在信号录取、角度录取、数据处理、方向图绘制方面全部实现了自动化,具有精度高、测量速度快、性能稳定、价格低廉的特点。     

Three-dimensional automatic mesh generation for hybrid electromagnetic simulations

Hybrid mesh generation is required for finite-difference time-domain/finite-element time-domain (FDTD/FETD) hybrid simulations. A combined approach is presented to automatically generate Cartesian/tetrahedral hybrid meshes for open and closed structures. This approach first generates a buffer zone that surrounds a target with specified tightness. The advancing-front technique with ldquosweep-and-retryrdquo is subsequently applied to generate an initial tetrahedral mesh that fills the buffer zone. Finally, the tetrahedral mesh undergoes a combined quality improvement procedure. Due to the low profile of the resulting tetrahedral mesh, the sparse Cholesky decomposition can be applied effectively to solve the resulting FETD matrix. Several examples are provided to demonstrate the main features and the performance of the proposed automatic mesh-generation method.     

Resequencing delay and buffer occupancy under the selective-repeatARQ

Consider a communication network that regulates retransmissions of erroneous packets by a selective-repeat (SR) automatic repeat request (ARQ) protocol. Packets are assigned consecutive integers, and the transmitter continuously transmits them in order until a negative acknowledgement or a time-out is observed. The receiver, upon receipt of a packet, checks for errors and returns positive/negative acknowledgement (ACK/NACK) accordingly. Only packets for which either NACK or time-out have been observed are retransmitted. Under SR ARQ, the receiver accepts packets that are out of order and must store them temporarily if it has to deliver them in sequence. The resequencing buffer requirements and the resulting packet delay constitute major factors in overall system considerations. The authors derive the distributions of the buffer occupancy and the resequencing delay at the receiver under a heavy traffic situation. This enables the network designer to determine how much buffer capacity at the receiver guarantees certain specified performance measures     

2D Mesh片上网络中交换机服务性能影响 的研究及其拓扑改进

 本文研究了交换机服务性能对2D Mesh片上网络的缓冲区资源和端到端延时的影响,发现在较低的丢包率的情况下,即使交换机能够提供很高的服务性能,却难以节省其所使用的缓冲区资源的现象.针对该现象,提出了一种基于星型子网的网状拓扑结构SSBM(Star-Subnet-Based-Mesh),在同样的网络规模以及丢包率的情况下,该种结构与2D Mesh结构相比具有更少的端到端通信延时,并且能够以较少的交换机服务性能为代价来节省较多的缓冲区资源,在较大程度上优化了2D Mesh片上网络的面积.     

The Characteristics of a Hydrogenated Amorphous Silicon Semitransparent Solar Cell When Applying n/i Buffer Layers

In this work, buffer layers with various conditions are inserted at an n/i interface in hydrogenated amorphous silicon semitransparent solar cells. It is observed that the performance of a solar cell strongly depends on the arrangement and thickness of the buffer layer. When arranging buffer layers with various bandgaps in ascending order from the intrinsic layer to the n layer, a relatively high open circuit voltage and short circuit current are observed. In addition, the fill factors are improved, owing to an enhanced shunt resistance under every instance of the introduced n/i buffer layers. Among the various conditions during the arrangement of the buffer layers, a reverse V shape of the energy bandgap is found to be the most effective for high efficiency, which also exhibits intermediate transmittance among all samples. This is an inspiring result, enabling an independent control of the conversion efficiency and transmittance.     

Transient self back-biased buffer for low-voltage high-performanceapplications in standard CMOS technologies

A low-voltage, high performance buffer suitable for implementation in standard CMOS technologies is proposed. The new buffer utilises the transient self back-bias (TSBB) technique to reduce electrically the threshold voltage of the output PMOS transistor, enhancing its performance. Simulations at 100 MHz and 0.9 V have shown that the TSBB buffer has a 35% speed advantage in the pull-up over the standard CMOS buffer. With only 5% increase in power dissipation