DC and AC characteristics of sub-50-nm MOSFETs with source/drain-to-gate nonoverlapped structure

A MOSFET structure with a nonoverlapped source/drain (S/D) to gate region was proposed to overcome the challenges in sub-50-nm CMOS devices. Key device characteristics were investigated by extensive simulation study. Fringing gate electric field through the spacer induces an inversion layer in the nonoverlap region to act as an extended S/D region. An oxide spacer is used to reduce parasitic gate overlap capacitance. A reasonable amount of inversion electrons were induced under the spacers. Internal physics, speed characteristics, short channel effects, and RF characteristics were studied with the nonoverlap distance at a fixed metallurgical channel length of 40 nm. The proposed structure had good drain-induced barrier lowering and V/sub T/ rolloff characteristics and showed reasonable intrinsic gate delay and cutoff frequency compared to those of an overlapped structure.     

50-nm fully depleted SOI CMOS technology with HfO/sub 2/ gate dielectric and TiN gate

In this paper, we demonstrate for the first time CMOS thin-film metal gate FDSOI devices using HfO/sub 2/ gate dielectric at the 50-nm physical gate length. Symmetric V/sub T/ is achieved for long-channel nMOS and pMOS devices using midgap TiN single metal gate with undoped channel and high-k dielectric. The devices show excellent performance with a I/sub on/=500 /spl mu/A//spl mu/m and I/sub off/=10 nA//spl mu/m at V/sub DD/=1.2 V for nMOSFET and I/sub on/=212 /spl mu/A//spl mu/m and I/sub off/=44 pA//spl mu/m at V/sub DD/=-1.2 V for pMOSFET, with a CET=30 /spl Aring/ and a gate length of 50 nm. DIBL and SS values as low as 70 mV/V nand 77 mV/dec, respectively, are obtained with a silicon film thickness of 14 nm. Ring oscillators with 15 ps stage delay at V/sub DD/=1.2 V are also realized.     

Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

Breakdown of universal mobility curves in sub-100-nm MOSFETs

We explore the breakdown of universal mobility behavior in sub-100-nm Si MOSFETs, using a novel three-dimensional (3-D) statistical simulation approach. In this approach, carrier trajectories in the bulk are treated via 3-D Brownian dynamics, while the carrier-interface roughness scattering is treated using a novel empirical model. Owing to the high efficiency of the transport kernel, effective mobility in 3-D MOSFETs with realistic Si-SiO/sub 2/ interfaces reconstructed from a Gaussian or exponential correlation function can be simulated in a statistical manner. We first demonstrate a practical calibration procedure for the interface mobility and affirm the universal behavior in the long channel limit. Next, effective mobility in ensembles of MOSFETs with a gate length down to 10 nm is investigated. It is found that the random-discrete nature of the Si-SiO/sub 2/ interface leads to a distribution of carrier mobility below the interface, which can deviate considerably from universal mobility curves when L/sub gate/<6/spl Lambda/, where /spl Lambda/ is the correlation length for the SiO/sub 2/ interface.     

High-frequency performance projections for ballistic carbon-nanotube transistors

A quasi-static approach is combined with a theory of ballistic nanotransistors to assess the high-frequency performance potential of carbon-nanotube field-effect transistors. A simple equivalent circuit, which applies in the ballistic limit of operation, is developed for the intrinsic device, and then employed to determine the behavior of the unity-current-gain frequency (f/sub T/) with gate voltage. The circuit is shown to reduce to the expected forms in the so-called "MOS" and "bipolar" limits. The f/sub T/ is shown to approach a maximum value of v/sub F//2/spl pi/L/spl ap/130 GHz/L (/spl mu/m) at high gate voltage, where v/sub F/ is the nanotube's Fermi velocity and L is the channel length, and to fall at low gate voltage due to the presence of source and drain electrostatic capacitances. The impact of the gate electrostatic capacitance on the f/sub T/ is also discussed. Numerical simulations on a "MOSFET-like" or "bulk-switched" carbon-nanotube transistor are shown to support the conclusions.     

On the reverse short‐channel effect and threshold voltage roll‐off controls for 90 nm node MOSFETs

Abstract

In order to let device designers tune the short channel behavior of MOSFETs, a method is proposed in this work to demonstrate how to use LDD (lightly doped drain) and pocket implants to control RSCE (reverse short channel effect) and threshold voltage (V_t ) roll‐off. The method is based on the process parameters and silicon data of the 90 nm node technology of UMC (United Microelectronics Corporation). With the help of computers, 17 different process conditions of 8 different gate lengths were simulated using ISE TCAD to collect V_t variation data. Four characteristics representing the short channel behaviors of the MOSFETs were designed and extracted from the simulated data. Their empirical equations were also established subsequently. After verification, those mathematical models were demonstrated to help device designers in choosing the most suitable LDD and pocket implant parameters to generate required V_t characteristics.     

Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs

Extrinsic resistance due to contacts and nonabrupt lateral extension doping profile can become a performance-limiter in ultrathin body double-gate FETs (DGFET). In this paper, two-dimensional device simulations are used to study and optimize the extrinsic resistance in a sub-20 nm gate length DGFET. For a given lateral doping gradient, the extension doping needs to be offset from the gate edge by an amount called the underlap. The current drive, and hence transistor performance, is maximized when the underlap is chosen in such a way as to balance the impact of nonabrupt doping on the short channel effects and series resistance. This optimization depends upon the maximum allowed off-state subthreshold leakage current and the electrostatic integrity of the device structure.     

Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.     

Intrinsic fluctuations in sub 10-nm double-gate MOSFETs introduced by discreteness of charge and matter

We study, using numerical simulation, the intrinsic parameter fluctuations in sub 10 nm gate length double gate MOSFETs introduced by discreteness of charge and atomicity of matter. The employed "atomistic" drift-diffusion simulation approach includes quantum corrections based on the density gradient formalism. The quantum confinement and source-to-drain tunnelling effects are carefully calibrated in respect of self-consistent Poisson-Schrodinger and nonequilibrium Green's function simulations. Various sources of intrinsic parameter fluctuations, including random discrete dopants in the source/drain regions, single dopant or charged defect state in the channel region and gate line edge roughness, are studied in detail.     

Optimization of single-gate carbon-nanotube field-effect transistors

The performance of Schottky-barrier carbon-nanotube field-effect transistors (CNTFETs) critically depends on the device geometry. Asymmetric gate contacts, the drain and source contact thickness, and inhomogenous dielectrics above and below the nanotube influence the device operation. An optimizer has been used to extract geometries with steep subthreshold slope and high I/sub on//I/sub off/ ratio. It is found that the best performance improvements can be achieved using asymmetric gates centered above the source contact, where the optimum position and length of the gate contact varies with the oxide thickness. The main advantages of geometries with asymmetric gate contacts are the increased I/sub on//I/sub off/ ratio and the fact that the gate voltage required to attain minimum drain current is shifted toward zero, whereas symmetric geometries require V/sub g/=V/sub d//2. Our results suggest that the subthreshold slope of single-gate CNTFETs scales linearly with the gate-oxide thickness and can be reduced by a factor of two reaching a value below 100 mV/dec for devices with oxide thicknesses smaller than 5 nm by geometry optimization.     

Channel length scaling in graphene field-effect transistors studied with pulsed current-voltage measurements

We investigate current saturation at short channel lengths in graphene field-effect transistors (GFETs). Saturation is necessary to achieve low-output conductance required for device power gain. Dual-channel pulsed current-voltage measurements are performed to eliminate the significant effects of trapped charge in the gate dielectric, a problem common to all oxide-based dielectric films on graphene. With pulsed measurements, graphene transistors with channel lengths as small as 130 nm achieve output conductance as low as 0.3 mS/μm in saturation. The transconductance of the devices is independent of channel length, consistent with a velocity saturation model of high-field transport. Saturation velocities have a density dependence consistent with diffusive transport limited by optical phonon emission.     

Self-aligned ballistic n-type single-walled carbon nanotube field-effect transistors with adjustable threshold voltage

Near ballistic n-type single-walled carbon nanotube field-effect transistors (SWCNT FETs) have been fabricated with a novel self-aligned gate structure and a channel length of about 120 nm on a SWCNT with a diameter of 1.5 nm. The device shows excellent on- and off-state performance, including high transconductance of up to 25 microS, small subthreshold swing of 100 mV/dec, and gate delay time of 0.86 ps, suggesting that the device can potentially work at THz regime. Quantitative analysis on the electrical characteristics of a long channel device fabricated on the same SWCNT reveals that the SWCNT has a mean-free-path of 191 nm, and the electron mobility of the device reaches 4650 cm(2)/Vs. When benchmarked by the metric CV/ I vs Ion/Ioff, the n-type SWCNT FETs show significantly better off-state leakage than that of the Si-based n-type FETs with similar channel length. An important advantage of this self-aligned gate structure is that any suitable gate materials can be used, and in particular it is shown that the threshold voltage of the self-aligned n-type FETs can be adjusted by selecting gate metals with different work functions.     

Three-dimensional electrostatic effects of carbon nanotube transistors

We explore the three-dimensional (3-D) electrostatics of planar-gate carbon nanotube field-effect transistors (CNTFETs) using a self-consistent solution to the Poisson equation with equilibrium carrier statistics. We examine the effects of the gate insulator thickness and dielectric constant and the source/drain contact geometry on the electrostatics of bottom-gated (BG) and top-gated (TG) devices. We find that the electrostatic scaling length is mostly determined by the gate oxide thickness, not by the oxide dielectric constant. We also find that a high-k gate insulator does not necessarily improve short-channel immunity because it increases the coupling of both the gate and the source/drain contact to the channel. It also increases the parasitic coupling of the source/drain to the gate. Although both the width and the height of the source and drain contacts are important, we find that for the BG device, reducing the width of the 3-D contacts is more effective for improving short channel immunity than reducing the height. The TG device, however, is sensitive to both the width and height of the contact. We find that one-dimensional source and drain contacts promise the best short channel immunity. We also show that an optimized TG device with a thin gate oxide can provide near ideal subthreshold behavior. The results of this paper should provide useful guidance for designing high-performance CNTFETs.     

Assessment of high-frequency performance limits of graphene field-effect transistors

High frequency performance limits of graphene field-effect transistors (FETs) down to a channel length of 20 nm have been examined by using self-consistent quantum simulations. The results indicate that although Klein band-to-band tunneling is significant for sub-100 nm graphene FETs, it is possible to achieve a good transconductance and ballistic on-off ratio larger than 3 even at a channel length of 20 nm. At a channel length of 20 nm, the intrinsic cut-off frequency remains at a few THz for various gate insulator thickness values, but a thin gate insulator is necessary for a good transconductance and smaller degradation of cut-off frequency in the presence of parasitic capacitance. The intrinsic cut-off frequency is close to the LC characteristic frequency set by graphene kinetic inductance (L) and quantum capacitance (C), which is about 100 GHz·μm divided by the gate length.      

Interfacial charge transfer in nanoscale polymer transistors

Interfacial charge transfer plays an essential role in establishing the relative alignment of the metal Fermi level and the energy bands of organic semiconductors. While the details remain elusive in many systems, this charge transfer has been inferred in a number of photoemission experiments. We present electronic transport measurements in very short channel (L < 100 nm) transistors made from poly(3-hexylthiophene) (P3HT). As channel length is reduced, the evolution of the contact resistance and the zero gate voltage conductance are consistent with such charge transfer. Short channel conduction in devices with Pt contacts is greatly enhanced compared to analogous devices with Au contacts, consistent with charge transfer expectations. Alternating current scanning tunneling microscopy (ACSTM) provides further evidence that holes are transferred from Pt into P3HT, while much less charge transfer takes place at the Au/P3HT interface. This article is published with open access at Springerlink.com     

Nanometer-scale analysis of current limited stresses impact on SiO/sub 2/ gate oxide reliability using C-AFM

A conductive atomic force microscope (C-AFM) has been used to analyze at a nanometer scale the impact of the current limitation on the breakdown (BD) of thin (<6 nm) SiO/sub 2/ gate oxides of metal-oxide-semiconductor (MOS) structures. The high-lateral resolution of the technique (/spl sim/10 nm) allows to get more insight in the BD phenomenology and to study, independently, the effect of the current limit on different post-BD oxide properties such as the oxide conductivity at the primary location where the event is triggered (S/sub 0/) and the size of the broken-down region (S/sub BD/). The results show that the conductivity at S/sub 0/, the total area affected by the BD and the structural damage of the oxide increase when a current limitation is not imposed during the electrical stress, leading to harder BD events. The results demonstrate that the C-AFM is a very suitable tool to perform a complete analysis of the BD phenomenology at such reduced scale.     

High-performance strained Si/SiGe pMOS devices with multiple quantum wells

This paper describes the fabrication and results of the electrical characterization of buried channel Si/SiGe pMOS devices using double and single quantum wells. The devices have been fabricated in an almost standard CMOS technology including shallow trench isolation, rapid thermal annealing, and standard Co/Ti silicidation. The incorporation of 15% and 32% channels provides a strong enhancement (up to 85%) in long-channel mobility. This increased mobility behavior is translated into a 55% higher on-state current for the long-channel devices and a 13% higher on-state current (V/sub gs/-V/sub T/= -1 V and V/sub ds/= -1.5 V) for devices down to L/sub mask/=70 nm while maintaining low leakage and good short-channel and drain induced barrier lowering behavior.     

Narrow-band correction of the residual amplitude modulation in frequency-modulation spectroscopy

We have developed a narrow-band controller in the MHz range, based on a field-programmable gate array. It is used to control the probe beam intensity in frequency-modulated spectroscopy experiments with an acoustooptic modulator. The residual amplitude modulation at the modulation frequency (2.5 MHz) is reduced by 50 dB. The first-harmonic detection of the signals is operated in saturation spectroscopy of I/sub 2/ at 514.5 nm and 501.7 nm. A reduction of the background noise and a large increase in the signal-to-noise ratio are obtained.     

Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application

We proposed "reverse-order source/drain formation with double offset spacer" (RODOS) structure for low-power and high-speed applications. Both simulation and experimental data were used to evaluate the potential of the structure. It showed improved performance in terms of poly-depletion effect, dc characteristics, gate delay (CV/I), switching energy (CV/sup 2/) and linearity (V/sub IP3/). It satisfied all the requirements of LOP and LSTP for 90 nm technology node in ITRS 2002. Simulation predicted 794 /spl mu/A//spl mu/m in on-current, 0.1 nA//spl mu/m in off-current, 65 mV/V in DIBL, 80 mV/dec in SS, 1.29 ps in gate delay, 198 GHz in f/sub T/ and 0.151 fJ in switching energy in addition to enhanced linearity. Finally, we confirmed the high feasibility and potential of the RODOS MOSFET's for low-power and high-speed applications such as an LNA in portable communication appliances.     

Memory effect of a polymer thin-film transistor with self-assembled gold nanoparticles in the gate dielectric

A self-assembled film of gold nanoparticles is integrated into the gate dielectric of an organic thin-film transistor to produce memory effects. The transistor is fabricated on a heavily doped n-type silicon (n/sup +/-Si) substrate with a thermally grown oxide layer of 100 nm thick. n/sup +/-Si serves as the gate electrode while the oxide layer functions as the gate dielectric. Gold nanoparticles as the floating gate for charge storage are deposited on the gate oxide by electrostatic layer-by-layer self-assembly method. A self-assembled multilayer of polyelectrolytes, together with a thin spin-coated poly(4-vinyl phenol) layer, covers the gold nanoparticles and separates them from the poly(3-hexyl thiophene) channel. Gold nanoparticles are charged or discharged with different gate bias so that the channel conductance is modulated. The memory transistor has an on/off ratio over 1500 and data retention time of about 200 s. The low-temperature solution-based process is especially suitable for plastic-based circuits. Therefore, the results of this study could accelerate achievement of cheap and flexible organic nonvolatile memories.