Phase Detectors/Phase Frequency Detectors for High Performance PLLs

Phase Frequency Detectors (PFDs) for use in clock distribution PLLs and Phase Detectors (PDs) for clock recovery PLLs that we have proposed recently to achieve high performance are reviewed and discussed. For the PFD, operating speed limitation and phase detecting characteristics are improved with two kinds of approaches, i.e., gate/logic design and configuration design. For the PD, a simple compensation technique to prevent the deterioration of the phase detecting characteristics by D-F/F and a new PD with delay cell of VCO replica are proposed to reduce the jitter caused by PD. By SPICE simulations and experiments, it is confirmed that the maximum operating speed of PFD is improved to more than twice of conventional one and the jitter caused by PD is reduced to a minimum level.     

10-Gb/s Inductorless CDRs With Digital Frequency Calibration

Two 10-Gb/s inductorless clock and data recovery (CDR) circuits using different gated digital-controlled oscillators (GDCO) are presented. A digital frequency calibration is adopted to save the power consumption and chip area. They have been fabricated in 0.18-$mu{hbox{m}}$ CMOS process. By using the complementary gating technique, the first CDR circuit occupies an active area of 0.16 ${hbox{mm}}^{2}$ and draws 36 mW from a 1.8 V supply. The measured rms jitter and peak-to-peak jitter is 8.5 ps and 42.7 ps , respectively. By using the quadrature gating technique, the second CDR circuit consumes an active area of 0.25 ${hbox{mm}}^{2}$ and its power consumption of 56 mW. The measured rms jitter and peak-to-peak jitter is 3.4 ps and 21.8 ps, respectively. The power of the second CDR circuit is higher than that of the first one but its jitter is reduced.      

10 Gb/s Linear Full-Rate CMOS Phase Detector for Clock Data Recovery Circuit

An improved linear full-rate CMOS 10 Gb/s phase detector is proposed. The improved phase detector overcomes the difficulties in realizing the full-rate operation by adding an I/Q splitter for the input data. Such a topology enlarges the pulse width of output signals to ease the full clock rate operation and the problem of the half period skew in the whole clock data recovery system. The proposed topology is able to provide a good linearity over a wider operating range of input phase offset compared to that of existing designs. The phase detector using the Chartered 0.18 μ m CMOS process is capable of operating up to a 10 GHz clock rate and 10 Gb/s input data for a 1.8 V supply voltage with 31 mW power consumption.     

Microwave Phase Detectors for PSK Demodulators

The simplest circuits for microwave phase detectors and their operation are described. Approximate analytical expressions for the output characteristic of the various circuits are given. Accurate prediction of detector performance is achieved with a large-signal nonlinear analysis using simultaneously the time- and frequency-domain approach. Applying the theory developed, the effects which cause deformation of the detector characteristic are investigated. Results of practical circuits operating in the 14-GHz range are given and compared with regard to phase-demodulator applications. A low-level phase detector is presented which permits 20-dB level variation with less than 2° phase error.     

A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector

A new mixed-mode binary phase shift keying (BPSK) demodulator is demonstrated using a half-rate bang-bang phase detector commonly used in clock and data recovery (CDR) applications. This demodulator can be used for new home networking applications using already installed CATV lines. A prototype chip realized by 0.18-mum CMOS process can demodulate 622-Mb/s data at 1.4-GHz carrier frequency. At this data rate, the demodulator core consumes 27.5 mW from a 1.8 V power supply while the core chip area is 210 times 150 mum². The transmission over 20-m CATV line using the prototype chip is successfully demonstrated.     

Properties of Frequency Difference Detectors

Among other applications, frequency-tracking loops are employed in digital-data receivers, either as a frequency-acquisition aid for phase-locked coherent reception, or as the sole carrier-frequency control for noncoherent reception. This article provides details of design and performance of the frequency-difference detector that lies at the heart of the loop.     

Coded Phase/Frequency Modulation

Channel coding combined with expanded signal sets has been shown [1] to improve error performance over uncoded modulation without expanding the bandwidth of the transmitted signals. In this paper, new coded modulation formats defined over an expanded set of signals varying both in phase and frequency are presented. The new schemes combine FSK and PSK modulation and make use of trellis coding and Viterbi decoding to improve error performance over uncoded modulation. The free Euclidean distance is calculated for several classes of codes, and upper bounds and simulation results are also presented for some simple codes. The spectral characteristics of the proposed coded modulation formats are evaluated and compared to conventional two-dimensional modulation formats. Differential encoding and various extensions of the basic scheme are also discussed.     

宽带集成检波器频率响应的补偿及阻抗匹配

本文简要介绍了在0.3千兆赫到12.4千兆赫内采用一个“T”型电路对检波管芯实现匹配,从而在通带内得到小于1.5的驻波比.叙述了采用“R-L”并联支路使检波器的频响起伏在整个通带内小于±0.3分贝的方法.这些方法可应用于相类似的宽带电路中以改善特性.     

Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery

A significant problem in phase-locked loop (PLL) timing and carrier extraction is the initial acquisition. Very narrow loop bandwidths are generally required to control phase jitter, and acquisition may depend on an extremely accurate initial VCO frequency (VCXO) or sweeping. We describe two simply implemented frequency detectors which, when added to the traditional phase detector, can effect acquisition even with very small loop bandwidths and large initial frequency offsets. The first is the quadricorrelator, previously applied to timing recovery by Bellisio, while the second is new, and called a rotational frequency detector. The latter, while limited to lower frequencies and higher signal-to-noise ratios, is suitable for many applications and can be implemented with simpler circuitry.     

一种新型数字鉴频／鉴相器的设计

介绍了一种数字鉴频／鉴相器的逻辑设计、电路设计、版图设计和工艺制作技术，设计的电路工作频率为８ＭＨｚ，鉴相灵敏度为０．１２Ｖ／ｒａｄ，鉴相范围达±２π。该电路具有可靠性好、稳定度高等特点，可广泛应用于数字锁相环电路中。     

A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays

A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-mum CMOS process, is presented. A fast lock time of 7.5 mus and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm² and consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.     

一种用于锁相环快速锁定的动态鉴频鉴相器

设计了一种用于电荷泵锁相(CPPLL)快速锁定的动态鉴频鉴相器(PFD).该PFD采用传统结构,利用开关延时动态D触发器预充电,复位时间内输入时钟边沿未发生丢失,有效地消除了盲区.基于TSMC 0.18μm CMOS工艺,用Cadence Spectre对其进行仿真验证.结果显示,采用新型PFD的锁相环,其锁定速度提高40.3%,频率范围达1 MHz～2 GHz.     

用于锁相环快速锁定的鉴频鉴相器设计

针对鉴频鉴相器(PFD)的盲区现象对锁相环路的锁定速度的影响,设计了一种PFD结构,可以实现锁相环路的快速锁定。该结构在传统PFD的基础上,利用内部信号的逻辑关系进行逻辑控制,其输出特性呈现非线性;在输入相位差大于π时,抑制了复位脉冲的产生,避免了输入时钟边沿的丢失,有效消除了盲区,加快了锁相环的锁定速度。设计采用SMIC 0.18μm标准CMOS工艺,采用全定制设计方法对该PFD结构进行了设计、仿真分析和验证。结果表明,采用该PFD结构的锁相环,在400 MHz工作频率下锁定时间为2.95μs,锁定速度提高了34.27%。     

A Class of Reduced-Complexity Viterbi Detectors for Partial Response Continuous Phase Modulation

Partial response continuous phase modulation (CPM) gives constant envelope digital modulation schemes with excellent power spectra. Both narrow main lobe and low spectral tails can be achieved. When these signals are detected in an optimum coherent maximum likelihood sequence detector (Viterbi detector), power efficient schemes can also be designed, sometimes at the expense of receiver complexity. This paper describes a general class of simple Viterbi detectors with reduced complexity compared to the optimum case. The key idea is that the approximate receiver is based on a less complex CPM scheme than the transmitted scheme. The asymptotically optimum reduced-complexity receiver is found for a variety of transmitted schemes and various complexity reduction factors, for a specific class of receivers and modulation indexes. A new distance measure is introduced for the performance analysis. Smooth schemes based on raised cosine pulses are analyzed and simulated for the case of simplified reception. A graceful performance degradation occurs with the reduction of complexity.     

Full-Rate Complex Orthogonal Space-Time Block Code for Multiple Antennas

In this paper, full-rate and complex orthogonal space-time block code (STBC) schemes for multiple antennas are proposed, and turbo code is employed as channel coding to improve the proposed STBC schemes performance further. Compared with full-diversity multiple antennas STBC schemes, the proposed schemes can implement full data rate, partial diversity and a smaller complexity. On the condition of the same system throughput and concatenation of turbo code, the proposed schemes have lower bit error rate (BER) than those low-rate and full-diversity code schemes.This work is supported by China Postdoctoral Science Foundation under grant No. 2005038242 and Chinese Jiangsu Planned Projects for Postdoctoral Research Funds. Xiangbin Yu received the M.S degrees in Communication and Information Systems from Hohai University, Nanjing, China, in 2001; and his Ph.D. in Communication and Information Systems in 2004 from National Mobile Communications Research Laboratory at Southeast University, China. Now he is working as a Postdoctoral Researcher in Information and Communication Engineering Postdoctoral Research Station at Nanjing University of Aeronautics and Astronautics, Nanjing, China. His research interests include multi-carrier digital communication, space-time coding, adaptive modulation and digital signal processing in communications. DaZhuan Xu received the M.S degrees and Ph.D. in Communication and Information Systems from Nanjing University of Aeronautics and Astronautics in 1986 and 2001, respectively. He is now a full professor in College of Information Science and Technology, Nanjing University of Aeronautics and Astronautics, Nanjing, China. Prof. Xu is a Senior Member of China Institute of Electronics (CIE). His research interests include digital communications, soft radio, coding theory, medical signal processing. Guangguo Bi was graduated from Nanjing Institute of Technology, Nanjing, China, in 1960. He is now a professor in the Department of Radio Engineering of Southeast University, Nanjing, China. Prof. Bi is a fellow and a member of the board of Director of the China Institute of Communications, and a senior member of IEEE. His research interests include digital communications, personal communications network, spread spectrum communications, and intelligent information processing. He has published more than 200 papers in above areas.     

Design of an Improved CMOS Phase/Frequency Detector

A complementary metal oxide semiconductor (CMOS) phase/frequency detector (PFD) is presented. An improved CMOS D-type master-slave flip-flop is described and adopted in the PFD. Higher speed and lower power operation is attributed to the reduced node capacitance. Charge-sharing phenomena are circumvented in the proposed flip-flop and PFD. The maximum frequency of operation of the PFD is analytically studied. Device-sizing equations, based upon a first-order approximation, for the PFD are derived. The proposed PFD shows improvements in both phase and frequency sensitivities at high operating frequencies. HSPICE simulations of a phase-locked loop (PLL) employing the improved PFD demonstrate a faster frequency acquisition. The PLL simulations also verify that the maximum operating frequency of the PFD is in agreement with our analytical results.     

Real-Domain Decoder for Full-Rate Full-Diversity STBC with Multidimensional Constellations

In this letter, we present a new maximum likelihood (ML) decoding algorithm for space time block codes (STBCs) that employ multidimensional constellations. We start with a lattice representation for STBCs which transforms complex channel models into real matrix equations. Based on the lattice representation, we propose a new decoding algorithm for quasiorthogonal STBCs (QO-STBC) which allows simpleML decoding with performance identical to the conventional ML decoder. Multidimensional rotated constellations are constructed for the QO-STBCs to achieve full diversity. As a consequence, for quasi-orthogonal designs with an arbitrary number of transmit antennas N (N ? 4), the proposed decoding scheme achieves full rate and full diversity while reducing the decoding complexity from ∂(M_c^N/2) to ∂(M_c^N/4) in a M_c-QAM constellation.     

Estimation of Frequency for AM/FM Models Using the Phase Vocoder Framework

This paper proposes an extension of the applicability of phase-vocoder-based frequency estimators for generalized sinusoidal models, which include phase and amplitude modulations. A first approach, called phase corrected vocoder (PCV), takes into account the modification of the Fourier phases resulting from these modulations. Another approach is based on an adaptation of the principles of the time-frequency reassignment and is referred to as the reassigned vocoder (RV). The robustness of the estimation against noise is studied, both theoretically and experimentally, and the performance is assessed in comparison with two state-of-the-art algorithms: an unmodified version of the reassignment method and a quadratically interpolated fast Fourier transform method (QIFFT).     

A Calibrated Phase/Frequency Detector for Reference Spur Reduction in Charge-Pump PLLs

This brief presents a new technique for minimizing reference spurs in a charge-pump phase-locked loop (PLL) while maintaining dead-zone-free operation. The proposed circuitry uses a phase/frequency detector with a variable delay element in its reset path, with the delay length controlled by feedback from the charge-pump. Simulations have been performed with several PLLs to compare the proposed circuitry with previously reported techniques. The proposed approach shows improvements over previously reported techniques of 12 and 16 dB in the two closest reference spurs.     

“一体化”模拟鉴频／鉴相器研究

本文介绍一种适用于微波锁相频率合成的新型电路—“一体化”鉴频鉴相器。这种电路功能独特,可以很好地完成从鉴频到鉴相的工作过程传递。这种器件的应用提高了环路的捕捉能力,加快了环路捕捉速度,增加了环路工作的可靠性。