Simple gate-to-drain overlapped MOSFETs using poly spacers for highimmunity to channel hot-electron degradation

Short n-channel MOSFETs with permanent poly spacers over the lightly doped drain (LDD) region are demonstrated to be effective in increasing the resistance to channel hot-electron-induced degradation. The hot-electron lifetime of the poly-spacer devices is two to three orders of magnitude longer than that of a conventional oxide-spacer device. This improvement is entirely due to the reduced electron trapping in the gate oxide under the sidewall spacer. The disadvantages of the poly-spacer devices, higher gate-to-drain overlap capacitance and weaker gate oxide integrity, can both be minimized to within 20% of those of the oxide-spacer device by a short oxidation before the formation of the poly spacer     

Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stress

Interface trap (N/sub IT/) generation and recovery due to broken /spl equiv/Si-H bonds at the Si/SiO/sub 2/ interface is studied during and after hot carrier injection (HCI) stress and verified by a two-dimensional reaction-diffusion model. N/sub IT/ generation and recovery characteristics do not correlate with channel hot electron (HE) density distribution (verified by Monte Carlo simulations). Anode hole injection, which is triggered by HE injection into the gate poly, and valence band hole tunneling, which is triggered for thinner oxides, must be invoked to properly explain experimental results. The observed hole-induced, not electron-induced, breaking of /spl equiv/Si-H bonds during HCI stress is also consistent with that for negative bias temperature instability stress.     

Transconductance increase due to charge trapping during hot-carrier stress of nMOSFETs

An unusual hot-carrier degradation mode characterised by a transconductance increase during hot-carrier ageing of nMOS transistors is analysed. By measuring the effects of hot-carrier stress on drain and substrate characteristics and applying alternate static injection phases performed at different gate regimes, it is proved that the degradation is mainly due to negative charge trapping in a localised region near the drain. The transconductance increase is explained in terms of an exchange of the dominant role between the damaged and undamaged portions of the channel. This model is fully corroborated by 2D device electric simulation results.     

A new LDD structure: total overlap with polysilicon spacer (TOPS)

The total overlap with polysilicon spacer (TOPS) structure, a fully overlapped lightly doped drain (LDD) structure, is discussed. The TOPS structure achieves full gate overlap of the lightly doped region with simple processing. TOPS devices have demonstrated superior performance and reliability compared to oxide-spacer LDD devices, with an order of magnitude advantage in current degradation under stress for the same initial current drive or 30% more drive for the same amount of degradation. TOPS devices also show a much smaller sensitivity to n^- dose variation than LDD devices. Gate-induced drain leakage is reported for the first time in fully overlapped LDD devices     

Role of hot-hole injection in hot-carrier effects and the small degraded channel region in MOSFET's

Drain avalanche hot-carrier (DAHC) injection, which imposes the most severe limitations on n-channel MOS device design, is investigated from the viewpoint of surface-state generation and its localized area in the channel. It is shown, using the charge pumping technique, that the surface states are mainly created by hot-hole injection, and its small degraded area stretches toward the source region with increased stress time. A remarkable correlation between the increase of surface-state density, transconductance degradation, and substrate current is also described. In addition, to clarify the role of hot-hole injection, p-channel devices, as well as n-channel devices, are used, and hot-hole injection is shown to create more surface states than hot-electron injection.     

Effect of Channel Width Shortening on the Stability of a-Si:H/nc-Si:H Bilayer Thin-Film Transistors

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V _on) and on-state current (I _on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V _on is observed, attributed to electron injection into the gate dielectric, followed by I _on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.     

Investigation of the threshold voltage turn-around effect in long-channel n-MOSFETs due to hot-carrier stress

In this paper, we have investigated the turn-around effect of the threshold voltage (V_th) shift in the case of an n-type long channel MOSFET during hot-carrier stress. This effect is explained by the interplay between interface states and oxide traps, i.e. by the partial compensation of the rapidly created oxide charges by the more slowly created interface states. Significant hole trapping is observed from the negative shift of the threshold voltage during the first seconds of stress. Afterwards, V_th has switched to the positive voltage direction due to the negative charging of interface traps after relatively long stress time. To analyze this phenomenon in detail, a refined extraction technique for the defect distribution from charge-pumping measurements has been employed. Additionally, the obtained results have been explained by our physics-based model of hot-carrier degradation which considers not only channel electrons but also secondary holes generated by impact ionization. In spite of the small hole contribution (compared to that of electrons) to the total defect creation, its impact on the threshold voltage shift is comparable with the electronic one. The reason behind this trend is that hole-induced traps are shifted towards the source, thereby more severely affecting the device behavior.     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

不同栅压应力下1.8V pMOS热载流子退化机理研究

本文详细研究了不同栅压应力下1.8V pMOS器件的热载流子退化机理.研究结果表明,随着栅压应力增加,电子注入机制逐渐转化为空穴注入机制,使得pMOS漏极饱和电流(I_dsat)、漏极线性电流(I_dlin)及阈值电压(V_th)等性能参数退化量逐渐增加,但在V_gs=90%*V_ds时,因为没有载流子注入栅氧层,使得退化趋势出现转折.此外,研究还发现,界面态位于耗尽区时对空穴迁移率的影响小于其位于非耗尽区时的影响,致使正向I_dsat退化小于反向I_dsat退化,然而,正反向I_dlin退化却相同,这是因为I_dlin状态下器件整个沟道区均处于非耗尽状态.     

Two-dimensional analysis of the breakdown mechanism in theetched-groove silicon permeable base transistor

A two-dimensional, two-carrier simulation of a uniformly doped etched-groove permeable-base transistor which includes models for impact ionization and for Auger and Shockley-Read-Hall recombination is reported. It was found that for high current densities the breakdown voltage was reduced by channel avalanche. This mechanism was associated with a strong accumulation of electrons and holes in the source access region. In this region, the gate current remained low but the injection of electrons in the channel was enhanced, resulting in a degradation of the drain conductance and frequency performance     

Investigation of interface traps in LDD pMOST's by the DCIV method

Interface traps in submicron buried-channel LDD pMOSTs, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOSTs. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high     

Channel width dependence of AC stress on bulk nMOSFETs

Channel width dependence of AC stress was investigated. OFF-state stress generated negative interface traps, positive oxide charges, and neutral traps in the whole channel region. Comparison of drain currents of parasitic and main MOSFET during OFF-state indicates that more defects were generated on channel edge than near its center. During ON-state stress, electrons were dominantly trapped in the neutral traps near channel edge. These results cause degradation due to AC stress to become increasingly severe as W is scaled down. The operating voltage to guarantee 10-year lifetime decreased as width decreased. The above results show that electron trapping in neutral traps near the channel edge induce severe degradation on narrow nMOSFET during AC stress. Therefore, degradation of channel edge during AC stress is an importantly considered in narrow nMOSFET.     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

Device reliability study of AlGaN/GaN high electron mobility transistors under high gate and channel electric fields via low frequency noise spectroscopy

A set of different short term stress conditions are applied to AlGaN/GaN high electron mobility transistors and changes in the electronic behaviour of the gate stack and channel region are investigated by simultaneous gate and drain current low frequency noise measurements. Permanent degradation of gate current noise is observed during high gate reverse bias stress which is linked to defect creation in the gate edges. In the channel region a permanent degradation of drain noise is observed after a relatively high drain voltage stress in the ON-state. This is attributed to an increase in the trap density at the AlGaN/GaN interface under the gated part of the channel. It was found that self-heating alone does not cause any permanent degradation to the channel or gate stack. OFF-state stress also does not affect the gate stack or the channel.     

HALO结构pMOSFETs在V_g=V_d/2应力模式下应力相关的热载流子退化

研究了超薄栅(2 .5 nm )短沟HAL O- p MOSFETs在Vg=Vd/ 2应力模式下不同应力电压时热载流子退化特性.随着应力电压的变化,器件的退化特性也发生了改变.在加速应力下寿命外推方法会导致过高地估计器件寿命.在高场应力下器件退化是由空穴注入或者电子与空穴复合引起的,随着应力电压的下降器件退化主要是由电子注入引起的.最后,给出了两种退化机制的临界电压并在实验中得到验证     

Effects of high field injection on the hot carrier induceddegradation of submicrometer pMOSFET's

The interaction between the hot carrier (HC) induced pMOSFET's degradation and the Fowler-Nordheim (FN) injection is investigated. It has been found that the FN injection is an efficient method to recover pMOSFET's from the HC induced degradation. This is achieved by removing some of the trapped electrons from the oxide and forming positive charges along the channel. The relative importance of these two factors is determined. The contribution of the interface states created by FN injection is negligible, since they are acceptor-like and not charged during pMOSFET's operation. The positive charges increase the lifetime of a recovered pMOSFET by requiring more electron trapping to compensate their effects on the threshold voltage. They also enhance the magnitude of punchthrough voltage. The effects of FN injection on the HC trapping kinetics are discussed. Under our experimental conditions, the new trapping sites created by FN injection are negligible, compared with the as-grown traps. When a recovered pMOSFET is stressed again, its degradation rate is not higher than that of a fresh pMOSFET. This allows FN injection to be used repeatedly and we can therefore control the pMOSFET's degradation within a given range     

Relationship between MOSFET degradation and hot-electron-induced interface-state generation

Device degradation due to hot-electron injection in n-channel MOSFET's is mainly caused by mobility degradation and reduced mobile charges in the channel introduced by interface-state generation. With the use of simple gradual-channel approximation (GCA), a linear relationship is derived between the threshold shift, relative transconductance reduction, and the number of interface states generated. This model provides a link between the electrical characteristics of a degraded device and its physical damages and, therefore, is a vital tool in the study of hot-electron-induced device degradation mechanisms.     

Hot-carrier degradation phenomena in lateral and vertical DMOS transistors

The hot-carrier degradation behavior of both a lateral and a vertical integrated DMOS transistor is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Upon hot-carrier stress, two different, and competing degradation mechanisms are present: channel electron mobility reduction due to interface trap formation, and injection and trapping of hot holes in the accumulation region of the transistor. It will be shown that the latter mechanism is absent in the vertical DMOS.     

New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs

In this letter, we report new findings in the relation between channel hot-carrier (CHC) degradation and gate-oxide breakdown (BD) in short-channel nMOSFETS biased at V/sub G/>V/sub D/. We observe that the time-to-BD is strongly reduced in the hot carrier regime and that although the channel hot-electron injection into the oxide occurs mainly at the drain side, stress-induced leakage current (SILC) generation and oxide BD always occur at the source side. The results of these measurements indicate that not solely the energy of the injected electrons but also the oxide electric field is determinant in the oxide BD process.     

A comparison of the effects of cobalt-60 γ ray irradiation on DPSA bipolar transistors at high and low injection levels

We investigate the γ-ray total dose induced degradation of double polysilicon self-aligned (DPSA) bipolar NPN transistors at low dose rate. Through comparing the measured results in low- and high-level injection regions, we find that the main irradiation damages related defects in two regions are quite different. In the case of lower emitter-base (E-B) bias, the damage is mainly localized in E-B interface region. For high-level injection, excess base current mainly results from radiation induced defects in intrinsic base region. Furthermore, a phenomenological model based on qualitatively analytical calculation is adopted to explain the experimental results.