Fabrication of high-aspect-ratio polymer nanochannels using a novel Si nanoimprint mold and solvent-assisted sealing

We present a low cost nanofabrication method to fabricate high-aspect-ratio (HAR) polymer nanochannels using a novel silicon nanoimprint mold fabrication technique and a solvent-assisted sealing method. These nanofluidic channels are being developed for single biomolecule detection. The silicon nanoimprint mold fabrication process is based on the combination of anisotropic etching of silicon by potassium hydroxide (KOH) solution and the local oxidation of silicon (LOCOS) process. The resulting high-aspect-ratio silicon mold has smooth sidewalls owing to the anisotropic KOH etching process along the silicon crystalline geometry as well as the LOCOS process. The nanostructures in the nanoimprint molds that form the nanochannels can be easily controlled by the initial micropattern sizes defined using conventional UV lithography and the oxidation time, making this technique a practical solution for low cost and high-throughput HAR silicon nanoimprint mold fabrication. Nanoimprint molds having aspect ratios of more than 1:5.5 (width: 200 nm, height: 1.1 μm, length: 1 cm) were successfully fabricated. Nanoimprinting technique was used to create poly(methyl methacrylate) (PMMA) nanotrenches out of this nanoimprint mold. A novel solvent-assisted sealing technique was developed in order to seal the HAR PMMA nanotrenches. This technique enables the generation of nanochannels with various nanoscale dimensions without the need for complicated and expensive nanolithography tools.     

几种基于MEMS的纳米梁制作方法研究

特征尺度在纳米量级的梁结构是多种纳机电器件的基本结构.提出了几种基于MEMS技术的纳米梁制作方法,通过利用MEMS技术中材料与工艺的特性实现单晶硅纳米梁的制作.在普通(111)硅片上,利用各向异性湿法腐蚀对(111)面腐蚀速率极低的特性,通过干法与湿法腐蚀相结合制成厚度在100 nm以下的纳米梁.该方法不使用SOI硅片,有效控制了成本.在(100)SOI硅片上,通过氧化减薄的方法得到厚度在100 nm以下的多种纳米梁,由于热氧化的精度高,一致性好,该方法重复性与一致性均较好.在(110)SOI硅片上,利用硅的各向异性腐蚀特性以及(110)硅片的晶向特点,制作宽度在100 nm以下的纳米梁,梁的两个侧面是(111)面.     

Pre-buried mask wet etching for suspended silicon microstructures applied in rocking mass micro-gyroscope

Microsystem Technologies - A pre-buried mask method to fabricate suspended silicon microstructures by using pure wet etching in TMAH solution is presented in this paper. Pre-buried mask method...     

Fabrication of metallic microstructures by electroplating usingdeep-etched silicon molds

A new technology is presented here to fabricate three-dimensional micromachined metal structures. The microstructures are manufactured by electroplating in deep-etched silicon structures followed by a separation from their mold. Up to 140-μm-deep silicon structures with vertical sidewalls are realized by an anisotropic plasma etching process producing the mold for electroplating. An etching gas mixture of SF_6s and CBrF₃ is used to achieve both an anisotropic etching behavior by protective film formation of CF₂ -radicals and high etching rates. The anisotropy is due to photoresist masking, which enhances the polymer formation. The vertical trenches are electroplated from the trench base filling the structures uniformly to the substrate surface. By avoiding overplating across the whole substrate the resulting structures are suitable for micromechanical devices. If needed, released microstructures from the silicon mold can be obtained by direct lift-off     

Quasi-static drainage in a network of nanoslits of non-uniform depth designed by grayscale laser lithography

A method is reported to fabricate silicon–glass nanofluidic chips with non-uniform channel depths in the range 20–500 nm and micrometer resolution in width. The process is based on grayscale laser lithography to structure photoresist in 2.5 dimensions in a single step, followed by a reactive ion etching to transfer the resist depth profile into silicon. It can be easily integrated in a complete process flow chart. The method is used to fabricate a network of interconnected slits of non-uniform depth, a geometry mimicking a nanoporous medium. The network is then used to perform a pressure step-controlled drainage experiment, i.e., the immiscible displacement of a wetting fluid (liquid water) by a non-wetting one (nitrogen). The drainage patterns are analyzed by comparison with simulations based on the invasion percolation algorithm. The results indicate that slow drainage in the considered nanofluidic system well corresponds to the classical capillary fingering regime.     

A novel fabrication method based on an after thermal oxidation process for the realization of silicon-beams with normative polygon cross sections shapes

This paper presents a novel method to obtain structures with normative polygon cross section (PCS) shapes in a single crystal silicon substrate. A combination of wet etching and an after thermal oxidation (ATO) technique was used to fabricate several novel, complex structures with PCS shapes, which can hardly be fabricated by traditional wet etching. Based on such an innovative method, this paper proposes and develops three varieties of PCS silicon-beams. The subsequent experiment of fabricating silicon-beams with hexagonal sections has been taken as an example to validate the technique principle. Furthermore, the dimension parameters of the fabricated structures have been tested. Through this novel fabrication method, the sidewall arris of the fabricated silicon-beams can be maintained due to the protection of the ATO SiO₂ layers, the arris disfigurement of the silicon-beam decreases dramatically and the quality of the silicon-beam is improved greatly.     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

改进的硅各向异性腐蚀GPU并行模拟

硅各向异性腐蚀过程复杂,采用元胞自动机模拟硅各向异性腐蚀非常耗时。为了加速腐蚀模拟过程,研究了基于图形处理器(GPU)进行硅的各向异性腐蚀模拟。针对串行算法直接并行化方法存在加速效率低等问题,提出了一个改进的并行模拟方法。该方法增加了并行部分的负载,减少了内存管理的开销,从而提高了加速性能。实验证明该方法能够获得较理想的加速比。     

Fabrication of Cylindrical Nanopores and Nanopore Arrays in Silicon-On-Insulator Substrates

Electron-beam lithography and reactive ion etching were used to process silicon-on-insulator substrates for the fabrication of single cylindrical high-aspect-ratio solid-state nanopores and high-packing-density nanopore arrays. Minimum pore diameters of 40 nm were readily achieved with a high yield. The electrolyte concentration dependence of ion transport through single nanopores was measured for pores with diameters ranging from 40 to 140 nm. Measured single-nanopore conductances in high salt concentrations were compared to a simple model using a cylindrical resistance path and bulk solution conductivity. Electrochemical impedance spectroscopy was used to study the ac response of the device.     

Towards a versatile DRIE: silicon pit structures combined with electrochemical etch stop

A novel approach for fabricating low-pitch arrays of silicon membranes on standard CMOS wafers by combining deep-reactive ion etching (DRIE) and electrochemical etching (ECE) techniques is presented. These techniques have been used to fabricate membrane-based sensors and sensor arrays featuring different membrane sizes on a single wafer with a well defined etch stop. The described procedure is particularly useful in cases when the usage of SOI wafers is not an option. The combination of a grid-like mask pattern featuring uniform-size etch openings for the DRIE process with a reliable ECE technique allowed to fabricate silicon membranes with sizes ranging from 0.01 mm/sup 2/ to 2.2 mm/sup 2/. The development of this new method has been motivated by the need to design a compact n-well-based calorimetric sensor array, where the use of a standard ECE technique would have significantly increased the overall size of the device.     

基于金硅原电池保护电容加速度计的制作

提出并实现了一种利用SoI结合金硅原电池保护和反熔丝制作电容式加速度计的新工艺方法。该工艺用SoI顶层硅制作梁和上电极,用衬底制作质量块。采用DRIE从正面刻蚀形成释放孔,TMAH腐蚀实现质量块的释放,在TMAH腐蚀过程中利用金硅原电池保护实现梁和表面极板的保护。在TMAH腐蚀完成前,反镕丝保持断开状态,腐蚀完成后,击穿反镕丝形成导通状态。通过测量金和硅的极化曲线得到60℃25%TMAH中实现原电池保护的金硅面积比不小于5∶1。成功制作成电容式加速度计结构,释放前后梁宽度均在9.4～10μm范围内,表明原电池保护有效。击穿后反熔丝并联导通电阻为5～25 kΩ之间。     

Fabrication of a high aspect ratio nanoporous array on silicon

In this study, a simple method for the fabrication of high aspect ratio silicon nanoporous arrays is developed. A N-type silicon wafer is used as the substrate material. A micro-scale pattern of the desired porous array is transferred to the front surface of the silicon wafer by photolithography after which the wafer is placed in a home-made fixture to efficiently expel the etching generated air and promptly hold the back-side illumination light. A halogen lamp is used as the light source for backside illumination to enhance the electron–hole pair generation. An anodization process is then carried out using a new etchant consisting of hydrofluoric acid and mixed EtOH and EMSO surfactant to effectively polish the pore surfaces and sharpen the tips of the etched pores. A nanochannel array with a nano-tip of 61.4?nm is obtained.     

高灵敏度谐振式微加速度传感器的设计与制作

为提高加速度传感器灵敏度,提出一种新的加速度敏感机制,并基于此原理设计了一种新的微机械谐振式加速度传感器结构.分析了加速度传感器的数学模型及影响灵敏度的关键参数,并以此为依据对传感器结构参数进行优化设计.采用扩散硅层作为谐振子,提高器件性能的同时简化了制作工艺,利用KOH溶液湿法腐蚀硅在各晶向上的各向异性,实现了支撑梁...     

Study of black silicon obtained by cryogenic plasma etching: approach to achieve the hot spot of a thermoelectric energy harvester

In this paper, we study the enhanced absorption properties of micro/nano structured silicon surface under incident electromagnetic illumination and its capacity to convert light into heat. We simulate the optical reflectance of three-dimensional micro/nano silicon cones of different dimensions and under different electric field incident angles (θ _i ). According to the favorable simulation results, we fabricate black silicon with conical microstructures that exhibits excellent anti-reflectivity behavior. Plasma etching under cryogenic temperatures is used for this purpose in an inductively coupled plasma-reactive ion etching reactor. The reflectance of the black silicon is measured to be approximately 1?% in the optical wavelength range, by using an integrating sphere coupled to a calibrated spectrometer. Furthermore, a device integrating a resistance temperature detector in a black silicon area is developed in order to investigate its efficiency as a photo-thermal converter.     

Membrane microcantilever arrays fabrication with PZT thin films for nanorange movement

Lead zirconate titanate (PZT) piezoelectric thin films have been prepared by sol-gel method to fabricate microcantilever arrays for nano-actuation with potential applications in the hard disk drives. In order to solve the silicon over-etching problem, which leads to a low production yield in the microcantilever fabrication process, a new fabrication process using DRIE etching of silicon from the front side of the silicon wafer has been developed. Silicon free membrane microcantilevers with PZT thin films of 1 μm in thickness have been successfully fabricated with almost 100% yield by this new process. Annealing temperature and time are critical to the preparation of the sol-gel PZT thin film. The fabrication process of microcantilever arrays in planar structure will be presented. Key issues on the fabrication of the cantilever are the compatible etching process of PZT thin film and the compensation of thin film stress in all layers to obtain a flat multi-layer structure.     

Process development of precision surface micro-machining using mechanical abrasion and chemical etching

 A process that is capable of micro-machining the surface of both metallic and silicon materials has been developed. The process is based on mechanical abrasion of the surface using a very sharp and hard tool followed by chemical etching in some instances. The most critical parameter for the mechanical abrasion process is the thrust force which essentially dictates the mode of cutting. Experiments were performed using a specially built precision programmable machine with sub-micrometer feed resolution to identify the optimum operating conditions to obtain satisfactory cutting. By carefully adjusting the feed of the tool, pockets could also be machined quite successfully. In order to demonstrate the flexibility of the process, a miniature face was machined on both silicon and brass. The micro-machining process presented in this work can also be used to fabricate micro-molds as well as micro-grooves. Received: 24 August 2001/Accepted: 7 November 2001     

A combinative technique to fabricate hot embossing master for PMMA tunneling sensors

A combinative approach of anisotropic bulk etching and modified plasma etching has been successfully employed in a single wafer to fabricate silicon masters for the hot embossing process. The masters hold both pyramid pits and positive profile sidewalls with smooth surfaces and steep angles. The SiO₂ layer is utilized as a etching mask with the aid of photoresist in three steps of photolithography patterning. The first polymethyl-methacrylate (PMMA)-based tunneling transducer with polymer membrane structures is fabricated by hot embossing replication with the silicon master. Consequently, the exponential relations between tunneling currents and applied deflection voltages are also reported.This work is partially supported by grants NSF/LEQSF (2001–04)-RII-02, DARPA DAAD19–02–1-0338, and NASA (2002)-Stennis-22.     

一种具有广泛适应性的微机械加工方法研究

研究了一种具有广泛适应性的微机械制造方法,该方法可用于制备各种不同的器件,包括硅微陀螺仪、加速度计、剪切应力传感器以及光开关等.利用该方法,制备了硅微陀螺仪,并给出了所制备的硅微陀螺仪的性能测试结果,同时分析了利用该制备方法制备各种不同器件时,工艺流程对器件性能的影响,重点讨论了硅-玻璃阳极键合、减薄工艺以及深刻蚀所形成的侧壁质量,包括侧壁垂直度、侧壁杂质等因素对器件性能的影响.     

有机溶剂在P型宏多孔硅电化学腐蚀中的应用研究

近年来,多孔硅以其良好的光学、热学、电学以及机械特性使其在微传感器技术领域得到广泛的应用,电化学腐蚀多孔硅的各种方法与原理引起越来越多的关注。研究了P型硅的电化学腐蚀过程中,在腐蚀溶液中使用有机溶剂对多孔硅的制备、速率、成孔机理等方面的影响。研究发现,在分别使用有机溶剂二甲基甲酰胺(DMF)和二甲基亚砜(DMSO)的氢氟酸(HF)腐蚀溶液中,可以制备出孔壁光滑、具有高深宽比的高质量P型宏多孔硅,并发现了一种快速腐蚀P型宏多孔硅的方法,得到高达1900μm/h的腐蚀速率,这有助于提高多孔硅在微传感器批量化生产应用中的效率。在涌流模型基础上,分析了有机溶剂的氧化性和质子(H)提供能力,以及在P型多孔硅快速腐蚀过程中的作用。     

A high Q micromachined single crystal silicon bulk mode resonator with pre-etched cavity

In this paper, a novel method of fabricating micromachined single crystal silicon bulk mode resonators is demonstrated. The most distinguishing feature of this method is that the resonator structure is fabricated and released simultaneously in the end of the process, as a cavity for structure release is pre-etched in the substrate layer. The advantages of this process include: simplifying the fabrication process by fabricating and releasing the device structure simultaneously; enhancing fabrication yield through eliminating the sacrificial release step needed for existing process. The complete process has been validated and prototypes have been fabricated. The transmission performance of a 4.13 MHz Lamé mode square resonator fabricated using this method is presented, with a quality factor of 8,400 in air and exceeding one million at pressure of 0.11 mbar, respectively.