Removal of stacking faults in Ge grown on Si through nanoscale openings in chemical SiO2

Nucleation and eventual coalescence of Ge islands, grown out of 5 to 7 nm diameter openings in chemical SiO₂ template and epitaxially registered to the underlying Si substrate, have been shown to generate a low density of threading dislocations (?10⁶ cm^− 2). This result compares favorably to a threading dislocation density exceeding 10⁸ cm^− 2 in Ge films grown directly on Si. However, the coalesced Ge film contains a relatively high density of stacking faults (5 × 10⁷ cm^− 2), and subsequent growth of GaAs leads to an adverse root-mean-square roughness of 36 nm and a reduced photoluminescence intensity at 20% compared to GaAs grown on Ge or GaAs substrates. Herein, we find that annealing the Ge islands at 1073 K for 30 min before their coalescence into a contiguous film completely removes the stacking faults. However, the anneal step undesirably desorbs any SiO₂ not covered by existing Ge islands. Further Ge growth results in a threading dislocation density of 5 × 10⁷ cm^− 2, but without any stacking faults. Threading dislocations are believed to result from the later Ge growth on the newly exposed Si where the SiO₂ has desorbed from areas uncovered by Ge islands. The morphology and photoluminescence intensity of GaAs grown on the annealed Ge is comparable to films grown on GaAs or Ge substrates. Despite this improvement, the GaAs films grown on the annealed Ge/Si exhibit a threading dislocation density of 2 × 10⁷ cm^− 2 and a minority carrier lifetime of 67 ps compared to 4 to 5 ns for GaAs on Ge or GaAs substrates. A second oxidation step after the high temperature anneal of the Ge islands is proposed to reconstitute the SiO₂ template and subsequently improve the quality of Ge film.     

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.     

High quality Ge epitaxial layers on Si by ultrahigh vacuum chemical vapor deposition

Flat, relaxed Ge epitaxial layers with low threading dislocation density (TDD) of 1.94 × 10⁶ cm^− 2 were grown on Si(001) by ultrahigh vacuum chemical vapor deposition. High temperature Ge growth at 500 °C on 45 nm low temperature (LT) Ge buffer layer grown at 300 °C ensured the growth of a flat surface with RMS roughness of 1 nm; however, the growth at 650 °C resulted in rough intermixed SiGe layer irrespective of the use of low temperature Ge buffer layer due to the roughening of LT Ge buffer layer during the temperature ramp and subsequent severe surface diffusion at high temperatures. Two-dimensional Ge layer grown at LT was very crucial in achieving low TDD Ge epitaxial film suitable for device applications.     

Low threading dislocation Ge on Si by combining deposition and etching

Blanket and selective Ge growth on Si is investigated using reduced pressure chemical vapor deposition. To reduce the threading dislocation density (TDD) at low thickness, Ge deposition with cyclic annealing followed by HCl etching is performed. In the case of blanket Ge deposition, a TDD of 1.3 × 10⁶ cm^− 2 is obtained, when the Ge layer is etched back from 4.5 μm thickness to 1.8 μm. The TDD is not increased relative to the situation before etching. The root mean square of roughness of the 1.8 μm thick Ge is about 0.46 nm, which is of the same level as before HCl etching. Further etching shows increased surface roughness caused by non-uniform strain distribution near the interface due to misfit dislocations and threading dislocations. The TDD also becomes higher because the etchfront of Ge reaches areas with high dislocation density near the interface. In the case of selective Ge growth, a slightly lower TDD is observed in smaller windows caused by a weak pattern size dependence on Ge thickness. A significant decrease of TDD of selectively grown Ge is also observed by increasing the Ge thickness. An about 10 times lower TDD at the same Ge thickness is demonstrated by applying a combination of deposition and etching processes during selective Ge growth.     

Performance study of InAs/GaAs quantum dot covered by graded InxGa1 − xAs layer

InAs/GaAs quantum dots (QDs) with graded In_xGa_1 − xAs strained-reducing layer (SRL) are grown by metal-organic chemical vapor deposition, the effects of Indium (In) composition and thickness in In_xGa_1 − xAs on QD morphological characteristics and optical properties are investigated. Compared with In_xGa_1 − xAs SRL with fixed In content, gradient In_xGa_1−xAs SRL can further improve the growth quality of InAs QDs, enhance luminescence intensity and extend emission spectrum toward longer wavelength.     

Effect of GaAs substrate misorientation on InxGa1 − xAs crystalline quality and photovoltaic performance

This paper presents the quality of In_xGa_1 − xAs (0 < x < 0.2) layers grown on GaAs substrate with different miscut angle (2° and 15°) by metal organic chemical vapor deposition. The crystalline quality of In_xGa_1 − xAs layers was found to strongly depend on indium content and substrate misorientation. The In_0.16Ga_0.84As solar cells with PN structure were grown on a 2°- and 15°-off GaAs substrates. It was found that the photovoltaic performance of In_0.16Ga_0.84As solar cell grown on 2°-off GaAs substrate was better than that of In_0.16Ga_0.84As grown on a 15°-off GaAs substrate, because the In_xGa_1 − xAs films grown on 15°-off GaAs substrate shows a highly strain relaxation in active layer of solar cell, which causes the high dislocation density at the initial active layer/In_xGa_1 − xAs graded layer interface.     

Epitaxial growth of relaxed germanium layers by reduced pressure chemical vapour deposition on (110) and (111) silicon substrates

The growth of Ge on (110) and (111) oriented Si substrates is of great interest to enhance the mobility of both holes and electrons in complementary metal oxide semiconductor transistors. However, the quality of thick, relaxed Ge layers grown epitaxially on these surfaces is usually much lower than similar layers grown on (100) Si, resulting in both higher defect densities (i.e. threading dislocations and stacking faults) and rougher surfaces. In this work we have investigated the growth of Ge layers on (110) and (111) Si substrates by reduced-pressure chemical vapour deposition using a two temperature process. We have found that the combination of suppressing the Ge seed layer roughness and high temperature post-growth annealing can reduce the rms surface roughness of (110) Ge layers to below 2 nm and the threading dislocation density to below 1 × 10⁷ cm^− 2. Thick (111) Ge layers were found to exhibit a very high density of stacking faults, that could not be reduced by post-growth annealing and a higher rms surface roughness of around 12 nm, which was limited by the Ge seed layer.     

Effect of layer thickness on structural quality of Ge epilayers grown directly on Si(001)

A study of Ge epilayer growth directly on a Si(001) substrate is presented, following the two temperature Ge layer method. In an attempt to minimize the overall thickness while maintaining a good quality Ge epilayer, we have investigated the effect of varying the thickness of both the low and high temperature Ge layers, grown at 400 °C and 670 °C, respectively, by reduced pressure chemical vapor deposition. We find that the surface of the low temperature (LT) seed layer has a threading dislocation density (TDD) to the order of 10¹¹ cm^− 2. On increasing the LT layer thickness from 30 nm to 150 nm this TDD decreases by a factor of 2, while its roughness doubles and degree of relaxation increases from 82% to 96%. Growth of the high temperature (HT) layer reduces the TDD level to around 10⁸ cm^− 2, which is also shown to decrease with increasing layer thickness. Both the surface roughness and degree of relaxation reach stable values for which increasing the thickness beyond about 700 nm has no effect. Finally, annealing the HT layer is shown to reduce the TDD, without affecting the degree of relaxation. However, unless a thick structure is used the surface roughness increases significantly on annealing.     

The effect of helium ion implantation on the relaxation of strained InGaAs thin films

Previous work on pseudomorphic SiGe on Si has shown that a significant reduction in the threading dislocation density can be achieved through appropriate ion beam processing. Helium ion implantation was used in an analogous study to induce strain relaxation within strained pseudomorphic InGaAs layers on GaAs through the intentional introduction of subsurface damage without the introduction of surface nucleated dislocations and their associated threading segments. Wafers of fully-strained 28 nm thick films of In_0.24Ga_0.76As were separately implanted with helium doses of 5 × 10¹⁴, 2 × 10¹⁵, and 1 × 10¹⁶ cm⁻² at 25 keV. These wafers became substrates for additional InGaAs film growth. The final InGaAs films always exhibited lower residual strain as compared to films grown directly on a control substrate of non-implanted GaAs. The broadening of the X-ray peaks indicates an increase in dislocation density within the InGaAs films and the strain relaxation was found to occur with a significant increase in surface roughness. This result stands in contrast to related work on SiGe films on Si where a reduction of the threading dislocation density within a SiGe film was observed. The reaction of the InGaAs/GaAs structure and materials to ion irradiation, with local disturbance to the stoichiometry, could preclude the use of ion beam techniques for realizing a reduction in threading dislocation density during strain relaxation.     

Effects of low temperature ZnO and MgO buffer thicknesses on properties of ZnO films grown on (0001) Al2O3 substrates by plasma-assisted molecular beam epitaxy

We investigated the structural properties of Zn-polar ZnO films with low temperature (LT) ZnO and MgO buffer layers grown by plasma-assisted molecular beam epitaxy on (0001) c-Al₂O₃ substrates using X-ray diffraction and transmission electron microscopy (TEM). The effects of MgO buffer layer thickness and LT ZnO buffer layer thickness were also examined. The optimum thicknesses for better crystal quality were 8 and 40 nm. One-pair and two-pair LT ZnO/MgO buffer layers were employed, and the changes in the structural properties of the high-temperature (HT) ZnO films using such buffer layers were studied. Contrary to the general tendency of c-ZnO films, the HT ZnO films on the LT ZnO/MgO buffer layers showed higher full width at half maximum (FWHM) values for X-ray rocking curves (XRCs) with (0002) reflection than those with (101?1) reflection. Compared with the one-pair LT ZnO/MgO buffer layers, the FWHM values of (0002) XRCs markedly decreased, whereas those of (101?1) XRCs slightly increased due to the insertion of one more pair of LT ZnO/MgO buffer layers into the previous film with one-pair LT ZnO/MgO buffer layers. The cross-sectional TEM observations with the two-beam condition confirmed that the screw dislocation was the dominant threading dislocation type—a finding that agreed well with the XRC results. On the basis of the plan-view TEM observations, the densities of the total threading dislocations for the HT ZnO films with the one- and two-pair LT ZnO/MgO buffer layers were determined as 2.3 × 10⁹ cm^− 2 and 1.6 × 10⁹ cm^− 2, respectively. The results imply that the crystal quality of Zn-polar ZnO films can be improved by two-pair LT ZnO/MgO buffer layers, and types of threading dislocations can be modified by adjusting the buffer system.     

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10⁷ cm^− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III-V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.     

Crystalline quality and photovoltaic performance of InGaAs solar cells grown on GaAs substrate with large-misoriented angle

This article reports the quality of In_xGa_1−xAs (0 < x < 0.2) layers grown on 15°-off GaAs substrate by metalorganic chemical vapor deposition. The crystalline quality of the In_xGa_1−xAs epilayers is determined by x-ray reciprocal space mapping (RSM). From the RSM results, the crystalline quality of In_xGa_1−xAs epilayers grown with small indium composition (x < 0.11) is better than that of large indium composition (x > 0.11) due to the small strain relaxation. The crystalline quality of In_xGa_1−xAs epilayer is found to strongly depend on indium content. The photovoltaic performance of p-n structure In_0.16Ga_0.84As solar cell shows the lower device performance, because the In_xGa_1−xAs films grown on 15°-off GaAs substrate show a large strain relaxation in the active layer of solar cell. It results in dislocation defects created at the initial active layer/In_xGa_1−xAs graded layer interface. The performance of In_0.16Ga_0.84As solar cell with p-n structure can be significantly improved by the p-i-n structure.     

Growth and characterization of germanium epitaxial film on silicon (001) using reduced pressure chemical vapor deposition

High quality germanium (Ge) epitaxial film is grown directly on silicon (001) substrate using a “three-step growth” approach in a reduced pressure chemical vapor deposition system. The growth steps consist of sequential low temperature (LT) at 400 °C, intermediate temperature ramp (LT-HT) of ~ 6.5 °C/min and high temperature (HT) at 600 °C. This is followed by post-growth anneal in hydrogen at temperature ranging from 680 to 825 °C. Analytical characterizations have shown that the Ge epitaxial film of thickness ~ 1 μm experiences thermally induced tensile strain of 0.20% with a threading dislocation density of < 10⁷ cm^− 2 under optical microscope and root mean square roughness of ~ 0.9 nm. Further analysis has shown that the annealing time at high temperature has an impact on the surface morphology of the Ge epitaxial film. Further reduction in the RMS roughness can be achieved either through chemical mechanical polishing or to insert an annealing step between the LT-HT ramp and HT steps.     

Nanoscale interfacial engineering to grow Ge on Si as virtual substrates and subsequent integration of GaAs

We have demonstrated the scalability of a process previously dubbed as Ge “touchdown” on Si to substantially reduce threading dislocations below 10⁷/cm² in a Ge film grown on a 2 inch-diameter chemically oxidized Si substrate. This study also elucidates the overall mechanism of the touchdown process. The 1.4 nm thick chemical oxide is first formed by immersing Si substrates in a solution of H₂O₂ and H₂SO₄. Subsequent exposure to Ge flux creates 3 to 7 nm-diameter voids in the oxide at a density greater than 10¹¹/cm². Comparison of data taken from many previous studies and ours shows an exponential dependence between oxide thickness and inverse temperature of void formation. Additionally, exposure to a Ge or Si atom flux decreases the temperature at which voids begin to form in the oxide. These results strongly suggest that Ge actively participates in the reaction with SiO₂ in the void formation process. Once voids are created in the oxide under a Ge flux, Ge islands selectively nucleate within the void openings on the newly exposed Si. Island nucleation and growth then compete with the void growth reaction. At substrate temperatures between 823 and 1053 K, nanometer size Ge islands that nucleate within the voids continue to grow and coalesce into a continuous film over the remaining oxide. Coalescence of the Ge islands is believed to result in the creation of stacking faults in the Ge film at a density of 5 × 10⁷/cm². Additionally, coalescence results in films of 3 µm thickness having a root-mean-square roughness of 8 to 10 nm. We have found that polishing the films with dilute H₂O₂ results in roughness values below 0.5 nm. However, stacking faults originating at the Ge-SiO₂ interface and terminating at the Ge surface are polished at a slightly reduced rate, and show up as 1 to 2 nm raised lines on the polished Ge surface. These lines are then transferred into the subsequent growth morphology of GaAs deposited by metal-organic chemical vapor deposition. Room temperature photoluminescence shows that films of GaAs grown on Ge-on-oxidized Si have an intensity that is 20 to 25% compared to the intensity from GaAs grown on commercial Ge or GaAs substrates. Cathodoluminescence shows that nonradiative defects occur in the GaAs that spatially correspond to the stacking faults terminating at the Ge surface. The exact nature of these nonradiative defects in the GaAs is unknown, however, GaAs grown on annealed samples of Ge-on-oxidized Si, whereby annealing removes the stacking faults, have photoluminescence intensity that is comparable to GaAs grown on a GaAs substrate.     

The effect of growth temperature on the coaxial InxGa1 − xN/GaN nanowires grown by metalorganic chemical vapor deposition

We report on the growth of coaxial In_xGa_1 − xN/GaN nanowires (NWs) on Si(111) substrates by using pulsed flow metalorganic chemical vapor deposition. The coaxial In_xGa_1 − xN/GaN NWs were grown by a two step process in which the core (GaN) structure was grown at a higher temperature followed by the shell (In_xGa_1 − xN) structure at a lower temperature. Dense and well-oriented coaxial In_xGa_1 − xN/GaN NWs were grown with an average diameter and length of about 300 ± 50 nm and 1.5-2.0 μm, respectively. The coaxial In_xGa_1 − xN/GaN NW was confirmed by cathodoluminescence mapping and high-resolution transmission electron microscopy. It is proposed that the critical dissociation of precursors at an elevated growth temperature can lead to a clear formation of an outer-shell in coaxial In_xGa_1 − xN/GaN NWs.     

Characterization of AlxGa1−xAs layers grown on (100) GaAs by metallic-arsenic-based-MOCVD

We present the electrical and structural characterization of Al_xGa_1−xAs layers grown in a metallic-arsenic-based-MOCVD system. The gallium and aluminium precursors were the metal-organic compounds trimethylgallium (TMGa) and trimethylaluminium (TMAl), respectively. Al_xGa_1−xAs layers that were grown at temperatures less than 750 °C present a high electrical resistivity. Independent of the used III/V ratio the samples that were grown at temperatures greater that 750 °C were n-type with an electron concentration of around 10¹⁷ cm⁻³ and a carrier mobility of 2200 cm²/V-s. Chemical composition studies by SIMS exhibit the presence of silicon, carbon and oxygen as the main residual impurities. Silicon concentration of around of 10¹⁷ cm⁻³ is very close to the free carrier concentration determined by the Hall-van der Pauw measurements. Composition homogeneity and structural quality are demonstrated by Raman measurements. As the growth temperature is increased the layers compensation decreases but the Raman spectra show that the crystalline quality of the layers diminishes.     

Optical properties of nanocrystalline Ga1−xInxSb/SiO2 films

Ga_1−xIn_xSb (x=0.19, 0.38, 0.63) nanoparticles embedded in a SiO₂ matrix were grown on the glass substrates by radio-frequency magnetron co-sputtering. X-ray diffraction patterns strongly support the existence of nanocrystalline Ga_1−xIn_xSb in the SiO₂ matrix. The changes in binding energies with Ga_1−xIn_xSb nanocrystals deposition have been directly observed by X-ray photoemission spectroscopy, and these show the existence of Ga_1−xIn_xSb nanocrystals in the SiO₂ matrix. Room-temperature Raman spectra show that the Raman peaks of the Ga_1−xIn_xSb-SiO₂ composite film have a larger red-shift of about 95.3 cm⁻¹ (longitudinal-optical mode) and 120.1 cm⁻¹ (transverse-optical mode) than that of bulk GaSb, suggesting the existence of phonon confinement and tensile stress effects. Additionally, the room-temperature optical transmission data exhibit a large blue-shift with respect to that of the bulk semiconductor due to the strong quantum confinement effect.     

Reverse graded strain relaxed SiGe buffers for CMOS and optoelectronic integration

Reverse terrace graded buffers are proposed for high quality high Ge content Si_0.23Ge_0.77 buffers. The buffer structure allows the effects of applied thermal budget and grading rate to be separated and compared to previously reported reverse linearly graded virtual substrates. A reduction in threading dislocation density to 2.1 × 10⁶ cm^− 2 and an enhanced relaxation is found for these terrace graded structures of almost identical thickness and twice the strain gradient of the linear graded structures, whilst a smooth surface is retained with an rms roughness of just 1.9 nm.     

Monolithic integration of III-V optical interconnects on Si using SiGe virtual substrates

Working optical links epitaxially grown by atmospheric MOCVD and fabricated on Si via SiGe virtual substrates are demonstrated for the first time. The SiGe virtual substrates are graded from Si substrates to 100% Ge. Because of the 0.07% lattice mismatch between GaAs and Ge, high-quality GaAs-based thin films with threading dislocation densities <3×10⁶ cm^–2 were realized. The optical link consists of a GaAs PIN-LED and a GaAs PIN detector diode. A vertical-coupling scheme was utilized to couple devices with a Al_0.15Ga_0.85As waveguide. Waveguides of varying length, Y-junctions, and bends were fabricated. The straight waveguides exhibited loss of approximately 144 dB cm^–1.An erratum to this article can be found at     

Formation and structural characterization of nanocrystalline Si/SiC multilayers grown by hot filament assisted chemical vapor deposition using CH3SiH3 gas jets

We report on the formation and the structural characterization of nanocrystalline Si/SiC (nc-Si/SiC) multilayers on Si(100) by hot filament assisted chemical vapor deposition using CH₃SiH₃ gas pulse jets. Si rich amorphous SiC (a-Si_1 − xC_x, x ~ 0.33) was initially grown at the substrate temperature (T_s) of 600 °C with heating a hot filament at ~ 2000 °C. The following crystalline SiC layers were grown at T_s = 850 °C without utilizing a hot filament. When the a-Si_1 − xC_x layer was ultrathin (< 2 nm) on Si(100), this a-Si_1 − xC_x layer was transformed to a single epitaxial SiC layer during the subsequent SiC growth process. The Si{111} faceted pits were formed at the SiC/Si(100) interface due to Si diffusion processes from the substrate. When the thickness of the initial a-Si_1 − xC_x layer was increased to ~ 5 nm, a double layer structure was formed in which this amorphous layer was changed to nc-Si and nc-SiC was grown on the top resulting in the considerable reduction of the {111} faceted pits. It was found that nc-SiC was formed by consuming the Si atoms uniformly diffused from the a-Si_1 − xC_x layer below and that Si nanocrystals were generated in the a-Si_1 − xC_x layers due to the annealing effect during further multilayer growths.