90nm工艺下nMOS器件最大衬底电流应力特性

研究了90nm工艺条件下的轻掺杂漏(lightly-doped drain,LDD)nMOSFET器件最大衬底电流应力特性.在比较分析了连续不同电应力后LDD nMOSFET的GIDL(gate-induced drain leakage)电流变化后,发现当器件的栅氧厚度接近1nm,沟长接近100nm时,最大衬底电流应力不是电子注入应力,也不是电子和空穴的共同注入应力,而是一种空穴注入应力,并采用空穴应力注入实验、负最大衬底电流应力实验验证了这一结论.     

90nm工艺下nMOS器件最大衬底电流应力特性

研究了90nm工艺条件下的轻掺杂漏(lightly-doped drain,LDD)nMOSFET器件最大衬底电流应力特性.在比较分析了连续不同电应力后LDD nMOSFET的GIDL(gate-induced drain leakage)电流变化后,发现当器件的栅氧厚度接近1nm,沟长接近100nm时,最大衬底电流应力不是电子注入应力,也不是电子和空穴的共同注入应力,而是一种空穴注入应力,并采用空穴应力注入实验、负最大衬底电流应力实验验证了这一结论.     

0.8μm CMOS LDD器件可靠性实验和分析

针对实验中发现的亚微米LDD结构的特殊的衬底电流现象和退化现象,进行了二维器件数值模拟,解释了LDD器件退化的原因,最后提出了LDD器件的优化工艺条件。     

集成电路可制造性设计中器件参数的提取

分别采用流体力学模型和漂移扩散模型对不同沟道长度的NMOSFET进行衬底电流的提取,并以NMOSFET沟道长度和LDD注入峰值综合对器件特性的影响为研究内容,介绍了集成电路可制造性设计中器件参数的优化与提取。     

Halo LDD结构多晶硅薄膜晶体管的模拟研究

提出了多晶硅薄膜晶体管的一种Halo LDD新结构,这种结构是在基于LDD结构的基础上,在沟道靠近源、漏端引入高掺杂的Halo区.并利用工艺和器件模拟软件对该Halo LDD P-Si TFT的电学特性进行了分析,并将其与常规结构、LDD结构和Halo结构进行了比较.发现Halo LDD结构的P-si TFT能有效地降低泄漏电流、抑制阈值电压漂移和Kink效应;减少因尺寸减小后所带来的一系列问题.     

超深亚微米非对称Halo LDD低功耗新器件的研究分析

提出了一种新的器件结构--非对称Halo LDD低功耗器件,该器件可以很好地抑制短沟效应,尤其可以很好地改善DIBL效应、热载流子效应以及降低功耗等,是低功耗高集成度电路的优选结构之一.分析了非对称Halo LDD器件的主要特性,并将其与常规结构、非对称LDD结构、非对称Halo结构的器件进行了比较并进行了参数优化分析.     

N-LDMOS热载流子注入效应的分析和优化

研究了一种N-LDMOS器件的热载流子注入效应,分析了热载流子效应产生的机理、对器件性能以及可靠性的影响,提出了改进方法.为了降低此器件的热载流子注入效应,我们利用华润上华公司提供的ISE软件对N-LDMOS高压工艺进行模拟,根据模拟结果调整了器件结构,通过增大器件的场板长度、漂移区长度以及增加N阱与有源区的交叠长度等措施,使得相同偏置条件下,表征热载流子注入强度的物理量——器件衬底电流降为改进前的1/10,显著改善了该器件的热载流子注入效应.     

击穿18V的高压LDD PMOS器件的研制

从Synopsys TCAD的软件模拟出发，基于0．8μm标准CMOS工艺，通过重新设计高压N阱，以及优化器件LDD区域注入剂量，成功研制了栅长0．8μm击穿电压达到18V的LDD结构的高压PMOS器件，并实现了低高压工艺的兼容。研制的宽长比为18／0．8的PMOS器件截止电流在500pA以下，阚值电压为-1．5V，-10V栅压下饱和电流为-5．6mA，击穿电压为-19V。器件主要优点是关态漏电小，且器件尺寸不增加，不影响集成度，满足微显示像素驱动电路对高压器件的尺寸要求，另外与其他高压器件相比更容易实现，节约了成本。     

LDD-CMOS中ESD及其相关机理

LDD工艺是CMOS集成电路进入亚微米后应用最广泛的技术,该技术很好地改善了沟道电场分布,避免了在器件漏端的强场效应,在可靠性方面明显地提高器件及电路的热载流子寿命.然而,LDD结构的抗ESD的能力却大大降低了.文中通过实验和分析,研究了在ESD过程中,LDD gg-nMOS器件的Snapback对器件潜在损伤的影响,尤其对热载流子效应的影响.     

LDD-CMOS中ESD及其相关机理

LDD工艺是CMOS集成电路进入亚微米后应用最广泛的技术,该技术很好地改善了沟道电场分布,避免了在器件漏端的强场效应,在可靠性方面明显地提高器件及电路的热载流子寿命.然而,LDD结构的抗ESD的能力却大大降低了.文中通过实验和分析,研究了在ESD过程中,LDDgg nMOS器件的Snapback对器件潜在损伤的影响,尤其对热载流子效应的影响     

Hot-carrier injection suppression due to the nitride-oxide LDDspacer structure

The hot-carrier effects in silicon nitride lightly doped drain (LDD) spacer MOSFETs are discussed. It is found that the oxide thickness under the nitride film spacer affects the hot-carrier effects. The thinner the LDD spacer oxide becomes, the larger the initial drain current degradation becomes at the DC stress test and the smaller the stress time dependence becomes. After the DC stress test, reduced drain current recovers at room temperature. These phenomena are due to the large hot-carrier injection into the LDD nitride spacer, because the nitride film barrier height is much less than the silicon oxide barrier height. Therefore, it is necessary to form the LDD spacer oxide, in order to suppress the large hot-carrier injection in the nitride film LDD spacer MOSFET. The drain current shift mechanism in the nitride spacer MOSFETs is discussed, considering the lucky electron model     

Hot-electron-induced degradation of conventional, minimum overlap,LDD and DDD N-channel MOSFETs

Substrate current characteristics of conventional minimum overlap, DDD (double-diffused drain), and LDD (lightly doped drain) n-channel MOSFETs with various LDD n^- doses have been studied. Threshold voltage shift, transconductance degradation, and change of substrate current for these devices after stressing were also investigated. The minimum gate/drain overlap devices had the highest substrate current and the worst hot-electron-induced degradation. The amount of gate-to-n⁺ drain overlap in LDD devices was an important factor for hot-electron effects, especially for devices with low LDD n^- doses. The injection of hot holes into gate oxide in these devices at small stressed gate voltages was observed and was clearly reflected in the change of substrate current. The device degradation of low-doped LDD n-channel MOSFETs induced by AC stress was rather severe     

Optimization of LDD devices for cryogenic operation

The optimization of lightly doped drain (LDD) devices to maximize hot-carrier device lifetime at cryogenic temperature is studied. The hot-carrier-induced device degradation behavior and mechanisms of the various LDD and conventional devices are investigated. Carefully designed LDD devices can have better device reliability at low temperature compared to the conventional devices. However, the device lifetime is very short at low temperature for all the devices, and the difference in device lifetime between LDD and control devices is not appreciably large. The degradation behavior of both LDD and non-LDD devices at 77 K does not follow the simple behavior modeled by substrate current. For a given device, the maximum degradation is not observed at the bias condition for maximum substrate current. The optimum LDD design depends on the specific stressing bias conditions at 77 K     

An improved HCI degradation model for a VLSI MOSFET

An improved hot carrier injection (HCI) degradation model was proposed based on interface trap gen-eration and oxide charge injection theory. It was evident that the degradation behavior of electric parameters such as I_(dlin), I_(dsat), G_m and V_t fitted well with this model. Devices were prepared with 0.35μm technology and different LDD processes, I_(dlin) and I_(dsat) after HCI stress were analyzed with the improved model. The effects of interface trap generation and oxide charge injection on device degradation were extracted, and the charge injection site could be obtained by this method. The work provides important information to device designers and process engineers.     

Reduced hot-electron effects in MOSFET's with an optimized LDD Structure

A comparison of device degradation due to hot-electron injection is made for conventional MOSFET's and lightly doped drain (LDD) structures. The studies indicate that, for an optimized LDD structure, critical device parameters, such as threshold voltage, transconductance, and linear and saturated current drives, show significantly reduced degradation when subjected to accelerated life testing. These results imply long-term stability for LDD devices used in VLSI circuits.     

源漏轻掺杂结构多晶硅薄膜晶体管模拟研究

采用同型结模型模拟计算了源漏轻掺杂结构的关态漏析电流,同时考虑热电子效应修正漏极电流模拟结果,使漏极电流降低到10^-11A量级,晶体管的开关电流比值达到10^6量级,模拟研究掺杂区浓度和宽度与多晶硅薄膜晶体管开关电流比的变化关系。     

Design, modeling, and fabrication of subhalf-micrometer CMOS transistors

We have designed, modeled, and fabricated subhalf-micrometer CMOS transistors. Two-dimensional process and device modeling was exercised extensively to determine the critical process parameters for device optimization. Buried-channel behavior of the p-channel FET's has been analyzed. The effect of lightly doped drain (LDD) structure on punch through voltage was studied. p and n-channel FET's with physical gate length as short as 0.3 µm, were fabricated using e-beam lithography, LDD structure, and silicided source-drains. The experimental devices show high transconductance and long-channel characteristics.     

Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.     

Arsenic/phosphorus LDD optimization by taking advantage ofphosphorus transient enhanced diffusion for high voltage input/outputCMOS devices

Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFET's with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced, as compared to the one without TED. The reason is that the TED effect can yield a more graded n^- LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field and current flow distributions have been conducted. The phosphorus TED effects on transistor driving current and off-state leakage current are also investigated     

An experimental study on the short-channel effects in undergatedpolysilicon thin-film transistors with and without lightly doped drainstructures

Short-channel effects are studied for undergated polysilicon thin-film transistors (TFTs). Although a simple lightly doped drain (LDD) structure can minimize the effects, a much longer LDD region is required than in a bulk transistor. In addition to significant effects similar to bulk transistors, the leakage current is more affected by variations of the channel length and drain bias than it is in a bulk transistor due to the granular structures of the polysilicon films and the enhanced junction field in the fully depleted structure. As results, variations of the ON current, OFF current, and their ratio are dramatic without the LDD structure