小尺寸NMOS和PMOS SEU敏感性对比分析

使用软件模拟的方法对NMOS和PMOS的单粒子翻转(SEU)特性进行份真,通过在阱内外碰撞的两种情况下对小尺寸NMOS和PMOS的SEU敏感性进行对比可知,对于深亚微米阶段相同工艺的器件,在阱外碰撞时,NMOS一定比PMOS对SEU敏感;但对于阱内碰撞,NMOS和PMOS对SEU的敏感性要视具体情况而定.     

MOS器件的X射线辐照效应

研究了在10keVX射线辐照情况下，MOS器件的阈值电压随总剂量和剂量率的改变而变化的趋势。实验结果表明，辐照后，与用Co^60作为辐射源辐照所做实验结果明显不同的是，NMOS器件的阈值电压漂移幅度远大于PMOS器件的漂移幅度。文中对这种现象进行了讨论。     

快速稳定的CMOS电荷泵电路的设计

基于交叉耦合NMOS单元,提出了一种低压、快速稳定的CMOS电荷泵电路.一个二极管连接的NMOS管与自举电容相并联,对电路进行预充电,从而改善了电荷泵电路的稳定建立特性.PMOS串联开关用于将信号传输到下一级.仿真结果表明,4级电荷泵的最大输出电压为7.41 V,建立时间为0.85 μs.     

铁电电容工艺与标准CMOS工艺兼容性研究

在铁电存储器制备过程中,Pb(Zr0.52Ti0.48)O3(PZT)铁电薄膜需经历多次热处理,铁电电容工艺与标准CMOS工艺的集成加工过程中可能存在交叉污染。对PZT薄膜中的铅在不同温度下的挥发量进行了测定,在温度为400℃时有0.15×10-6铅挥发。同时进一步研究了铁电工艺对底层NMOS管、PMOS管和CMOS电路性能的影响。实验结果表明:PMOS管的性能所受影响较大,PMOS管子的跨导(gm)明显降低;而NMOS管的性能所受影响较小;CMOS电路的数字逻辑功能正常。     

NMOS晶体管高剂量率下总剂量辐照特性研究

采用商用标准0.6μm体硅CMOS工艺设计了不同宽长比、不同沟道长度及不同版图结构的非加固型NMOS晶体管作为测试样品.经高剂量60Coγ射线的总剂量辐照实验,讨论其在不同栅源偏置电压下的总剂量辐照特性.研究表明NMOS总剂量效应对辐照时栅源偏置电压敏感;辐照引起阈值电压的漂移随W/L的变化不明显;沟道长度及版图结构对NMOS管辐照后的源漏极间泄漏电流的影响显著.     

低功耗CMOS工艺中NMOS管阈值电压偏移的研究

研究了在LPLV CMOS工艺中，用表面沟PMOS管工艺使NMOS管的阈值电压发生偏移的问题。在使用表面沟PMOS管的LPLV CMOM工艺中，NMOS管的多晶栅中的杂质不能达到均匀的分布，导致阈值电压发生偏移。文章提出了三个解决方案，并对其可行性进行了研究。     

低压触发可控硅结构在静电保护电路中的应用

对LVTSCR(Low Voltage Triggered Silicon Controlled Rectifier)结构在深亚微米集成电路中的抗静电特性进行了研究.实验结果表明,LVTSCR结构的参数,如NMOS管沟道长度、P-N扩散区间距和栅极连接方式等,都对LVTSCR结构的静电保护性能有影响.利用优化的LVTSCR结构,获得了6000V以上的ESD失效电压.     

PMOS辐照检测传感器总剂量效应模型研究

根据PMOS辐照检测传感器在辐照时所产生的氧化层电荷(Qot)的两个不同模型,模拟计算了不同剂量条件下的亚阈值特性。结果表明,在满足一阶动力学方程下建立的Qot模型与实验结果较为吻合,并适用于更大范围的辐照剂量。此外,还讨论和计算了栅氧化层厚度、沟道掺杂浓度等参数对PMOS辐照检测传感器特性的影响。结果表明,栅氧化层厚度是影响阈值电压漂移量的主要因素。     

负偏置温度不稳定性导致单粒子瞬态脉冲的压缩与展宽

摘要：本文基于3D TCAD 器件模拟,研究了130nm体硅工艺下,负偏置温度不稳定性（NBTI）对单粒子瞬态（SET）脉冲的影响。研究结果表明：当粒子轰击高输入反相器的PMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断压缩,当粒子轰击低输入反相器的NMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断展宽。基于研究结果,本文首次提出：NBTI对粒子轰击NMOS管所产生的SET脉冲的影响已经十分严重,在进行抗辐照加固设计时必须考虑NBTI所造成的影响。     

PMOS管工艺参数对反相器SET效应的影响

研究了体硅CMOS工艺下数字集成电路的抗辐照特性。利用Synopsys公司的三维半导体器件模拟软件Sentaurus,对数字集成电路中的反相器电路进行单粒子瞬态(SET)效应仿真,分析PMOS管的各种工艺参数对反相器SET效应产生的脉冲电压的影响。研究结果表明,通过降低PMOS管的栅氧层厚度、n阱掺杂浓度、p+深阱掺杂浓度以及提高衬底浓度,可以有效地减小反相器SET脉冲电压的峰值和脉冲宽度。该研究结果对抗辐照数字集成电路设计具有一定的指导作用。     

Punchthrough behavior in short channel NMOS and PMOS 6H-siliconcarbide transistors at elevated temperatures

An experimental investigation of the effects of high temperature on short channel NMOS and PMOS transistors in 6H-SiC is reported. Punchthrough characteristics are presented and examined at room temperature and 300°C. The punchthrough current increases dramatically for scaled PMOS transistors at high temperature while the temperature dependence of electrical characteristics for short channel NMOS is small. The results presented in this paper also provide insight into design criteria for short channel silicon carbide (SiC) devices intended for operation at elevated temperatures     

MOS晶体管中辐照引起的陷阱正电荷的强压退火

电离辐射在 MOS结构的 Si O2 层中建立正陷阱电荷 ,这些正陷阱电荷在正强栅偏压( + 2 0 V)下迅速减少 ,这是由于正栅压引起硅衬底中的电子向 Si O2 层隧道注入 ,从而与陷阱正电荷复合 .正栅压退火不仅对 N沟 MOS结构非常有效 ,对 P沟 MOS结构也有一定的影响 .给出了辐照后的 NMOS和 PMOS晶体管在强正栅压下退火的实验结果 ,阐明了正栅压下的“隧道退火”机理 .     

The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs

This paper reports the influences of uniaxial mechanical stress on the reverse-biased source/drain to substrate junction leakage of state-of-the-art 65 nm CMOS transistors. For n-channel metal-oxide-semiconductor (NMOS) transistors, the band-to-band tunneling (BTBT) dominates the junction leakage current due to heavily doped junction and pocket implants. However, for p-channel metal-oxide-semiconductor (PMOS) transistors with embedded SiGe source/drain, the leakage current is found to result from both BTBT and generation current due to defects generated in the SiGe layer and at the SiGe/Si interface. A four-point bending technique is used to apply mechanical uniaxial stress on NMOS and PMOS devices along the longitudinal direction. It was found that the leakage current of both devices increases (decreases) with applied uniaxial compressive (tensile) stress, and that the strain sensitivity of the junction leakage of NMOS transistors is much weaker than that of PMOS transistors. By combining the bending technique with process strained Si (PSS) technology, additional stress was applied to NMOS and PMOS with high built-in stress to investigate the characteristics of junction leakage under extremely high uniaxial stress. It is shown that uniaxial tensile stress can both enhance the NMOS device performance and decrease the junction leakage. However, for the PMOS, there exists a tradeoff between boosting the transistor performance and decreasing the junction leakage current, so there is a limit in the amount of compressive stress that can be beneficially applied.     

CMOS／SIMOX和CMOS／BESOI的γ射线辐照特性比较

用薄膜ＳＩＭＯＸ（ＳｅｐａｒａｔｉｏｎｂｙＩＭｐｌａｎｔａｔｉｏｎｏｆＯＸｙｇｅｎ）、厚膜ＢＥＳＯＩ（ｆｆｅｎｄｉｎｇａｎｄＥｔｃｈ－ｂａｃｋＳｉｌｉｃｏｎＯｎＩｎｓｕｌａｔｏｒ）和体硅材料制备了ＣＭＯＳ倒相器电路，并用６０Ｃｏγ射线进行了总剂量辐照试验。在不同偏置条件下，经不同剂量辐照后，分别测量了ＰＭＯＳ、ＮＭＯＳ的亚阈特性曲线，分析了引起ＭＯＳＦＥＴ阈值电压漂移的两种因素（辐照诱生氧化层电荷和新生界面态电荷）。对ＮＭＯＳ／ＳＩＭＯＸ，由于寄生背沟ＭＯＳ结构的影响，经辐照后背沟漏电很快增大，经３００Ｇｙ（Ｓｉ）辐照后器件已失效。而厚膜ＢＥＳＯＩ器件由于顶层硅膜较厚，基本上没有背沟效应，其辐照特性优于体硅器件。最后讨论了提高薄膜ＳＩＭＯＸ器件抗辐照性能的几种措施。     

Total ionizing dose radiation effects on NMOS parasitic transistors in advanced bulk CMOS technology devices

In this paper, total ionizing dose effect of NMOS transistors in advanced CMOS technology are examined. The radiation tests are performed at ⁶⁰Co sources at the dose rate of 50 rad (Si)/s. The investigation''s results show that the radiation-induced charge buildup in the gate oxide can be ignored, and the field oxide isolation structure is the main total dose problem. The total ionizing dose (TID) radiation effects of field oxide parasitic transistors are studied in detail. An analytical model of radiation defect charge induced by TID damage in field oxide is established. The I-V characteristics of the NMOS parasitic transistors at different doses are modeled by using a surface potential method. The modeling method is verified by the experimental I-V characteristics of 180 nm commercial NMOS device induced by TID radiation at different doses. The model results are in good agreement with the radiation experimental results, which shows the analytical model can accurately predict the radiation response characteristics of advanced bulk CMOS technology device.     

Measurement of MOS current mismatch in the weak inversion region

Measures the current matching properties of MOS transistors operated in the weak inversion region. The authors measured a total of about 1400 PMOS and NMOS transistors produced in four different processes and report the results in terms of mismatch dependance on current density, device dimensions, and substrate voltage, without using any specific model for the transistor     

Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors

The merging of halo implants from the drain side and the source side creates a maximum in the magnitude of the threshold voltage and thus a minimum in the off-current in the metal-oxide-semiconductor transistors. This paper demonstrates that the halo implant from the drain side can cross-over to the source side and vice versa for the look-ahead transistor test structures (transistor test structures with gate length smaller than that of the target transistor). The phenomenon of the cross-over of halo implant is more readily observed in PMOS transistors compared to NMOS transistors because for the same mask gate length, the effective channel length of PMOS transistor tends to be smaller than that of NMOS transistor. The advantage of the cross-over of halo implants can be understood as follows. Since the hole mobility is smaller than the electron mobility in silicon, PMOS transistor tends to have smaller on-current (I_on) than NMOS transistor. The on-current can be increased by using PMOS transistor with smaller mask gate length compared to the NMOS transistor. However, this approach will make the PMOS transistor very sensitive to the statistical variation in the gate electrode length during manufacturing. By making use of the above reported phenomenon, PMOS transistor can be made shorter without running into manufacturing control problem, resulting in bigger I_on but the penalty is that the I_off will become significantly higher.