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提出了12管低功耗SRAM加固单元。基于堆叠结构,大幅度降低电路的泄漏电流,有效降低了电路功耗。基于两个稳定结构,可以有效容忍单粒子翻转引起的软错误。Hspice仿真结果表明,与相关加固结构相比,该结构的功耗平均下降31.09%,HSNM平均上升19.91%,RSNM平均上升97.34%,WSNM平均上升15.37%,全工作状态下均具有较高的静态噪声容限,表现出优秀的稳定性能。虽然面积开销平均增加了9.56%,但是,读时间平均下降14.27%,写时间平均下降18.40%,能够满足高速电子设备的需求。 相似文献
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提出了一种面向可容错应用的低功耗SRAM架构。通过对输入数据进行预编码,提出的SRAM架构实现了以较小的精度损失降低SRAM电路功耗。设计了一种单端的8管SRAM单元。该8管单元采用读缓冲结构,提升了读稳定性。采用打破反馈环技术,提升了写能力。以该8管单元作为存储单元的近似SRAM电路能够在超低压下稳定工作。在40 nm CMOS工艺下对电路进行仿真。结果表明,该8管单元具有良好的稳定性和极低的功耗。因此,以该8管单元作为存储单元的近似SRAM电路具有非常低的功耗。在0.5 V电源电压和相同工作频率下,该近似SRAM电路的功耗比采用传统6管单元的SRAM电路功耗降低了59.86%。 相似文献
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本文提出了一种新型的亚阈值10管SRAM单元,在130nm工艺下,本设计的SRAM容量
为6kb,最低可以工作在320mv的电压下。同时一系列的低电压的技术被运用到本SRAM的
设计中,使其能够工作在亚阈值电压下。反短沟效应和反窄沟效应提升了SRAM性能。新型
的脉冲产生电路产生理想的亚阈值脉冲,使得读操作更稳定。浮动的写位线有效地减小了待
机时的漏电。短的读位线使得读操作速度更快和更低功耗。最终流片后的测量表明这系列技
术在亚阈值区都是非常有效的,SRAM在320mv的电压下,工作频率800KHz,消耗功耗
1.94uw。 相似文献
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SRAM作为常用的存储器,在速度和功耗方面有一定的优势,但其较大的面积是影响成本的主要原因。文章设计了一种256×8位动态功能重构的SRAM模块,在完成基本SRAM存储功能的前提下,通过设置重构标志信号tag及附加的控制逻辑信号,复用基本SRAM模块存储资源,使系统完成FIFO的顺序存储功能。整个设计一方面拓展了基本存储体的功能,另一方面,FPGA验证结果显示:实施重构方案后同一块FPGA器件的硬件资源利用率明显提高了。最后,采用插入门控时钟的低功耗优化方案进行了DC综合,结果显示动态功耗降低了59.6%。经过“重构”的方式后,只增加了少量电路便可以实现动态数字电路的基本功能,一方面完成了功能上的拓展,另一方面提高了存储模块硬件资源的利用率,使SRAM具有了更高的性价比。 相似文献
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静态存储器(SRAM)功耗是整个芯片功耗的重要组成部分,并且大规模SRAM的仿真在芯片设计中也相当费时。提出了一种基于40 nm CMOS工艺、适用于FPGA芯片的SRAM单元结构,并为该结构设计了外围读写控制电路。仿真结果表明,该结构的SRAM单元在保证正确的读写操作下,静态漏电电流远远小于同工艺下普通阈值CMOS管构造的SRAM单元。同时,为了FPGA芯片设计时大规模SRAM功能仿真的需要,为SRAM单元等编写了verilog语言描述的行为级模型,完成了整个设计的功能验证。 相似文献
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Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-T4 write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 muW in leakage power. 相似文献
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Majid Moghaddam Somayeh Timarchi Mohammad Hossein Moaiyeri Mohammad Eshghi 《Circuits, Systems, and Signal Processing》2016,35(5):1437-1455
This paper presents a new nine-transistor (9T) SRAM cell operating in the subthreshold region. In the proposed 9T SRAM cell, a suitable read operation is provided by suppressing the drain-induced barrier lowering effect and controlling the body–source voltage dynamically. Proper usage of low-threshold voltage (L-\(V_{\mathrm{t}}\)) transistors in the proposed design helps to reduce the read access time and enhance the reliability in the subthreshold region. In the proposed cell, a common bit-line is used in the read and write operations. This design leads to a larger write margin without using extra circuits. The simulation results at 90 nm CMOS technology demonstrate a qualified performance of the proposed SRAM cell in terms of power dissipation, power–delay product, write margin, read access time and sensitivity to process, voltage and temperature variations as compared to the other most efficient low-voltage SRAM cells previously presented in the literature. 相似文献
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Bo Zhai Hanson S. Blaauw D. Sylvester D. 《Solid-State Circuits, IEEE Journal of》2008,43(10):2338-2348
In this paper, we present a deep subthreshold 6-T SRAM, which was fabricated in an industrial 0.13 mum CMOS technology. We first use detailed simulations to explore the challenges of ultra-low-voltage memory design with a specific emphasis on the implications of variability. We then propose a single-ended 6-T SRAM design with a gated-feedback write-assist that remains robust deep in the subthreshold regime. Measurements of a test chip show that the proposed memory architecture functions from 1.2 V down to 193 mV and provides a 36% improvement in energy consumption over the previously proposed multiplexer-based subthreshold SRAM designs while using only half the area. Adjustable footers and headers are introduced, as well as body bias techniques to extend voltage scaling limits. 相似文献
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Ghasem Pasandi Mohsen Jafari Mohsen Imani 《International Journal of Electronics》2013,100(10):1621-1633
This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM). 相似文献
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Aly R. E. Bayoumi M. A. 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2007,54(4):318-322
On-chip cache consumes a large percentage of the whole chip area and expected to increase in advanced technologies. Charging/discharging large bit lines capacitance represents a large portion of power consumption during a write operation. We propose a novel write mechanism which depends only on one of the two bit lines to perform a write operation. Therefore, the proposed 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a write operation. Experimental results using HSPICE simulation shows that the write power saving is at least 49%. Both read delay and static noise margin are maintained after carefully sizing the cell transistors 相似文献
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提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管.存取管的沟道长度小于下拉管的沟道长度.由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑"1".存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的"读"操作.背栅反馈同时增强了SRAM单元的静态噪声容限(SNM).该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积.对SRAM单元的读写速度和功耗做了仿真和讨论.该SRAM单元可以工作在0.5V电源电压下. 相似文献
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提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管. 存取管的沟道长度小于下拉管的沟道长度. 由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑“1" . 存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的“读”操作. 背栅反馈同时增强了SRAM单元的静态噪声容限(SNM). 该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积. 对SRAM单元的读写速度和功耗做了仿真和讨论. 该SRAM单元可以工作在0.5V电源电压下. 相似文献
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《IEEE transactions on circuits and systems. I, Regular papers》2010,57(1):93-104