Impact of the electron, proton and helium irradiation on the forward I–V characteristics of high-power P–i–N diode

2.5 kV/100 A high-power P–i–N diode was electron, proton and helium irradiated in a wide range of irradiation doses with irradiation energies in the MeV range. The resulting forward I–V curves were registered in the temperature range 30–125 °C to investigate the magnitude of the crossing point current of the I–V curves––I_XING. I_XING was found to decrease with increasing irradiation dose and to disappear at high doses for all three irradiation treatments with exception of ion irradiated diodes with defect peaks placed deeply into the anode region. Using a simple model based on the thermal and injection dependence of the carrier lifetime, the explanation of this effect is presented with the support of the non-isothermal 2-D device simulation of helium irradiated devices.     

A function-fit model for the hard breakdown I–V characteristics of ultra-thin oxides in MOS structures

A function-fit model for the hard breakdown current–voltage characteristics of ultra-thin oxides in metal–oxide–semiconductor structures based on the smoothing function concept is presented. The model is intended to capture the diode-like and resistance-like behaviours observed at low and high applied biases, respectively, by means of a simple, continuous and derivable function. These features make the proposed expression suited for circuit simulation environments. The effect of temperature on the model parameters is also analysed.     

Modeling of the I–V characteristics of high-field stressed MOS structures using a Fowler–Nordheim-type tunneling expression

The gate current–voltage characteristic of a high-field stressed metal-oxide-semiconductor structure with trapped charge within the insulator barrier is consistent with a Fowler–Nordheim-type tunneling expression. Instead of considering a correction for the cathode electric field as usual, we use an effective local electric field that takes into account the distortion of the oxide conduction band profile caused by the trapped charge. An energy level at the injecting interface, introduced as an optimization parameter of the model, controls the tunneling distance used for calculating the effective field. Trap generation in the oxide is induced by high-field constant current stress and subsequent electron trapping at different injection levels is monitored by measuring the associated flat band voltage shift. The model applies for positive gate injection regardless the stress polarity and the involved parameters are obtained by fitting the experimental data without invoking any particular theoretical model for the trapping dynamics. In addition, it is shown how the presented model accounts for consistently both the current–voltage and voltage–current characteristics as a function of the injected charge through the oxide.     

Analytic expression for the Fowler–Nordheim V–I characteristic including the series resistance effect

It is shown in this communication that the Fowler-Nordheim (FN) tunneling expression for the current-voltage (I-V) characteristic can be analytically inverted so that an exact expression for the voltage-current (V-I) characteristic can be obtained. The solution of the resulting implicit equation is found using the Lambert W function, i.e. the solution of the transcendental equation we^w = x. The reported expressions are supported by experimental I-V curves measured in thin (≈5 nm) SiO₂ films in MOS capacitors. The analysis includes the case of a tunneling oxide with a large series resistance. For practical purposes, a closed-form expression for W based on a Padé-type approximation is also provided.     

Determination of the dice forward I–V characteristics of a power diode from a packaged device and its applications

The forward voltage drop (V_F) of a power diode is an important electrical parameter for a power diode. Diode with excessive V_F can be due to either defects in wafer fabrication or soldering processes. To identify if the defects in soldering process is the root cause to excessive V_F, the obvious method will be the method to extract the series resistance from the diode. However, the present series resistance extraction methods are either inaccurate or requires extensive computation time, and they are not practical for failure analysis and process monitoring. In this work, a modified series resistance extraction method is developed. Experimental results showed that the modified method is accurate, and the computation time is short.     

An accurate mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs with single-channel boron implantation

In this paper we develop an analytical mobility model for the I–V characteristics of n-channel enhancement-mode MOSFETs, in which the effects of the two-dimensional electric fields in the surface inversion channel and the parasitic resistances due to contact and interconnection are included. Most importantly, the developed mobility model easily takes the device structure and process into consideration. In order to demonstrate the capabilities of the developed model, the structure- and process-oriented parameters in the present mobility model are calculated explicitly for an n-channel enhancement-mode MOSFET with single-channel boron implantation. Moreover, n-channel MOSFETs with different channel lengths fabricated in a production line by using a set of test keys have been characterized and the measured mobilities have been compared to the model. Excellent agreement has been obtained for all ranges of the fabricated channel lengths, which strongly support the accuracy of the model.     

Study of the electrical cycling stressed large area Schottky diodes using I–V and noise measurements

Large area commercial Al/n-Si Schottky diodes were subjected to an electrical cycling stress in order to cause degradation of diodes with local contact irregularities. Using the I–V characteristics and noise measurements in the frequency range of 10 Hz to 10 kHz at room temperature and using the corresponding equivalent circuit representation of degraded diodes, it has been shown that the latent leakage paths contribute to the degradation of the Schottky diodes under the test conditions. The results could be used to confirm that the ideality factor cannot be alone used as prediction tool of diode behavior under electrical cycling stress. The conclusion of this paper is that the results show that this kind of the stress test can be used as a screening test for diodes with latent leakage current paths.     

Analysis of I–V measurements on PtSi-Si Schottky structures in a wide temperature range

I–V Measurements on PtSi-Si Schottky structures in a wide temperature range from 90 to 350 K were carried out. The contributions of thermionic-emission current and various other current-transport mechanisms were assumed when evaluating the Schottky barrier height Φ₀. Thus the generation-recombination, tunneling and leak currents caused by inhomogeneities and defects at the metal-semiconductor interface were taken into account.

Taking the above-mentioned mechanisms and their temperature dependence into consideration in the Schottky diode model, an outstanding agreement between theory and experiment was achieved in a wide temperature range.

Excluding the secondary current-transport mechanisms from the total current, a more exact value of the thermionic-emission saturation current I_te and thus a more accurate value ofΦ_b was reached.

The barrier height Φ_b and the modified Richardson constant A^** were calculated from the plot of thermionic-emission saturation current I_te as a function of temperature too. The proposed method of finding Φ_b is independent of the exact values of the metal-semiconductor contact area A and of the modified Richardson constant A^**. This fact can be used for determination of Φ_b in new Schottky structures based on multicomponent semiconductor materials.

Using the experimentally evaluated value A^** = 1.796 × 10⁶ Am⁻²K⁻² for the barrier height determination from I–V characteristics the value of Φ_b = 0.881 ± 0.002 eV was reached independent of temperature.

The more exact value of barrier height Φ_b is a relevant input parameter for Schottky diode computer-aided modeling and simulation, which provided a closer correlation between the experimental and theoretical characteristics.     

Characterization of charge trapping in SiO2/Al2O3 dielectric stacks by pulsed C–V technique

In this work, charge trapping in SiO₂/Al₂O₃ dielectric stacks is characterized by means of pulsed capacitance–voltage measurements. The proposed technique strongly reduces the measurement time and, as a consequence, the impact of charge trapping on the measurement results. Flat band voltage shift and fast current transient during short stress pulses are systematically monitored and the centroid and the amount of the trapped charge are extracted using a first-order model.     

The effect of small-signal AC voltages on C–V characterization and parameter extraction of SiO2 thin films

The effect of different small-signal ac voltage amplitudes on C–V curves characterized by thin SiO₂ based p-type MOS capacitor with aluminum gate is reported. When the small-signal ac voltage is comparable to the gate bias, the thickness of SiO₂ thin films extracted from the accumulation capacitance is found to be independent of small-signal ac voltage amplitudes, but the flat band voltage shift and interface state density associated with the variation of depletion layer capacitance are dependent on small-signal ac voltage amplitudes. They all increase with the small-signal ac voltage amplitudes. The experimental results reveal that the optimum small-signal ac voltage should be less than 100 mV. The mechanisms involving the depletion layer changes with small-signal ac voltages in SiO₂ thin films are also discussed in this paper.     

Prediction of dielectric reliability from I–V characteristics: Poole–Frenkel conduction mechanism leading to √E model for silicon nitride MIM capacitor

Two assumptions lead to a correlation between the leakage mechanism of a dielectric and dielectric reliability: the degradation of the dielectric is a direct cause of the leakage current flowing through the dielectric and breakdown occurs after a critical charge has been forced through the dielectric. The field and temperature dependence of the leakage current mechanism then determine the voltage acceleration factor and the activation energy of TDDB experiments. This simple physical model describes the reliability of metal insulator metal (MIM) capacitors with PECVD SiN remarkably well. The current conduction mechanism is described by Poole–Frenkel theory, leading to a √E dependence of the time to breakdown on the applied electric field. The model predicts correctly the voltage acceleration factor and its temperature dependence and the activation energy.     

Predicting the process induced warpage of electronic packages using the P–V–T–C equation and the Taguchi method

A critical issue in the manufacturing of electronic packages is the warpage induced during the molding process as a result of differences in the shrinkage of the constituent materials. Package warpage causes serious problems such as the quality degradation of devices and yield loss in manufacturing processes. Loss of lead coplanarity happens due to package warpage and causes difficulty in device testing and surface mount assembly. Internal stresses associated with package warpage can also cause device failures such as die cracking, broken circuits and package cracking.Warpage in IC package has drawn intensive attention in the past. Although the effects of thermal shrinkage were extensively investigated in the literatures, the influence of the cure shrinkage on package warpage had received less attention. Accordingly, this study develops a numerical approach for generating more accurate predictions of the package warpage by taking the effects of both thermal shrinkage and cure shrinkage into account. A three-dimensional finite element model of the small outline package (TSOP) DBS-27P is constructed and the proposed numerical approach, which is based on the P–V–T–C (pressure–volume–temperature–conversion) equation and the CTEs (coefficients of thermal expansion) of the package materials, is employed to predict the warpage at each of its corners under various packaging processing conditions. Using the Taguchi method, the relative influences of the transfer pressure, the packing pressure, the mold temperature and the curing time on the degree of package warpage are identified and the optimal processing conditions are established. A series of experimental packaging trials are performed using the optimal processing conditions. It is found that the warpage of the actual package is in good agreement with that predicted numerically. Therefore, the accuracy of the proposed numerical approach is confirmed. Moreover, the results also demonstrate the capability of the Taguchi method to identify the optimal packaging processing parameters on the basis of a limited number of simulation runs.     

Changes in the characteristics of CuInGaSe2 solar cells under light irradiation and during recovery: degradation analysis by the feeble light measuring method

Changes in the characteristics of CuInGaSe₂ solar cells in response to light irradiation were investigated. Then these changes, which suggest long-term degradation, were clarified using the measurement technique by feeble light. The thin-film cell of this type is considered to be “ever stable”. A stable result over the short term was also obtained in the light accelerated test of 2-SUN performed in this experiment. On the other hand, it was found that the characteristics measured with feeble light show a remarkable change over time. As a result of measuring at 0.065–105 mW/cm² light intensity, the change rate of cell output power was so intense the measurement light was weak. This finding reflects the increase in an internal defect and suggests a possibility that light irradiation exerts the influence on long-term cell performance. Moreover, by measuring with feeble light, we found that the changed output recovers by reverse voltage application. The phenomenon of recovery up on comparatively low reverse voltage can be considered as an application for maintaining stability.     

Computer simulation and modeling of graded bandgap CuInSe2/CdS based solar cells

This paper proposes the graded bandgap absorber material, Cu_1-xAg_xIn_1-y-zGa_yAl_z Se/sub 2(1-u$/ -/sub w/)S_2uTe_2w (CIS*) multinary system, to improve the low open-circuit voltage (V_OC) seen in CuInSe₂/CdS solar cells, without sacrificing the short-circuit current density (J_sc). It also proposes a p-i-n model for the CuInSe₂/CdS solar cell, where the intrinsic region is the graded bandgap CIS*. Reflecting surfaces are provided at the p-i and n-i interfaces to trap the light in the narrow intrinsic region for maximum generation of electron and hole pairs (EHP's). This optical confinement results in a 25-40% increase in the number of photons absorbed. An extensive numerical simulator was developed, which provides a 1-D self-consistent solution for Poisson's equation and the two continuity equations for electrons and holes. This simulator was used to generate J-V curves to delineate the effect of different grading profiles on cell performance. The effects of a uniform bandgap, normal grading, reverse grading, and a low bandgap notch have been considered. Having established the inherent advantages to these grading profiles an optimal doubly graded structure is proposed with grading between 1.5 eV and 1.3 eV regions which has V_OC=0.86 V, η=17.9%, FF=0.79 and J_sc=26.3 mA/cm² compared to 0.84 V, 14.9%, 0.76, and 23.3 mA/cm², respectively, for the highest efficiency 1.4-eV uniform bandgap cell. Replacing the thick CdS(2.42 ev) layer assumed in our simulations with a wide gap semiconductor such as ZnO(3.35 ev) increases all current densities by about 5 mA/cm², and increases the optimal calculated efficiency from 17.9% to roughly 21% for a doubly graded structure with a thickness of 1 μm and bandgaps ranging from 1.3 eV to 1.5 eV     

Simulation and experimental results on the forward J–V characteristic of Al implanted 4H–SiC p–i–n diodes

In this work the forward J–V characteristics of 4H–SiC p–i–n diodes are analysed by means of a physics based device simulator tuned by comparison to experimental results. The circular devices have a diameter of 350 μm. The implanted anode region showed a plateau aluminium concentration of 6×10¹⁹ cm⁻³ located at the surface with a profile edge located at 0.2 μm and a profile tail crossing the n-type epilayer doping at 1.35 μm. Al atom ionization efficiency was carefully taken into account during the simulations. The final devices showed good rectifying properties and at room temperature a diode current density close to 370 A/cm² could be measured at 5 V. The simulation results were in good agreement with the experimental data taken at temperatures up to about 523 K in the whole explored current range extending over nine orders of magnitude. Simulations also allowed to estimate the effect of a different p⁺ doping electrically effective profile on the device current handling capabilities.     

The self-formatting barrier characteristics of Cu–Mg/SiO2 and Cu–Ru/SiO2 films for Cu interconnects

To substitute or to supplement diffusion barrier as reducing lateral dimension of interconnects, the alloying Mg and Ru to Cu was investigated as a self-formatting barrier in terms of their resistivity, adhesion, and barrier characteristics After annealing at 400 °C for 30 min, the resistivities of the Cu–0.7 at%Mg alloy and Cu–2.2 at%Ru alloy were 2.0 μΩ cm and 2.5 μΩ cm, respectively, which are comparable to that of Cu films. The adhesion was investigated by means of a sandwiched structure using the four point bending test. The interfacial debonding energy, which represents the adhesion, of Cu–Mg/SiO₂ was over 5.0 J/m², while those of the Cu–Ru/SiO₂ and Cu/SiO₂ interfaces were 2.2 J/m² and 2.4 J/m², respectively. The barrier characteristics of the alloy films were also investigated by the time-dependent dielectric breakdown test, using a metal–oxide–semiconductor structure, under bias-temperature stress. It was shown that the alloying of Mg made the lifetime seven times longer, as opposed to the alloying of Ru which made it shorter.     

CuInSe2薄膜太阳能电池非真空印刷制备技术研究

对CuInSe2(CISe)薄膜太阳能电池的吸收层进行了非真空印刷制备技术研究。使用机械化学法合成CISe前驱粉末,采用ethyl-cellulose作为分散试剂配置印刷浆,使用丝网印刷技术沉淀CISe吸收层,对沉淀的吸收层进行N2氛围的快速热退火处理,使用XRD、UV、SEM及J-V等手段对CISe吸收层进行了分析表征。结果表明:简单高效的机械化学法可获得主(112)晶向CISe前驱粉末;经丝网印刷并干燥后的CISe吸收层中含有大量有机分散剂,退火可蒸发有机分散剂并有效改善CISe结晶度,但过长的退火会增加晶体缺陷;实验制得一典型CISe薄膜太阳能电池的短路电流密度、开路电压、填充因子和转换效率分别为4.48mA/cm2、355mV、0.41和0.65%。     

Preparation of erbium ion-doped TiO2 films and the study of their photocatalytic activity under simulated solar light

A series of erbium ion-doped TiO₂ (Er³⁺-TiO₂) films were prepared by a sol-gel dip/spin coating method, and the effect of the dosage of erbium ion (0-2.0 mol%), the films coating layers (1-5 layers), and calcination temperature (400-700℃) on the film structure and photocatalytic activity were investigated in detail. The films were characterized by means of X-ray diffraction (XRD), scanning electron microscopy (SEM), thermal analysis (TG-DTG) and UV-Vis diffusive reflectance spectra (DRS). The results showed that the films were composed of anatase, and no other TiO₂ phases (rutile and brookite). With the increase of the erbium ion dosage, the crystal size decreased. Erbium ion doping could enhance the thermal stability of TiO₂ and inhibit the increase of the crystallite size. Meanwhile doping of erbium ions gave rise to three typical absorption peaks within the range of visible light (400-700 nm), locating at 490, 523, and 654 nm, attributed to the transition of 4f electrons. The higher calcination temperature led to higher crystallinity and bigger crystal grains. The photocatalytic performance of the films was evaluated by degradation of methyl orange solution under simulated solar light. The highest quality film we prepared was with 4 layers, 1.0 mol% dosage of erbium ion, and the calcination temperature of 500℃. With this film, the degradation percentage of 7.8 mg/L methyl orange solution was up to 53.3% under simulated solar light after 6 h photoreaction.     

As2S8平面波导：退火-光照-退火循环作用下折射率的变化及光传输特性

蒸发沉积态的非晶半导体As2S8薄膜在退火-饱和光照-退火循环处理下,其折射率变化存在可逆。而对于在退火-非饱和光照-退火的连续处理,发现As2S8薄膜折射率先增加达到最大值,然后在退火作用下才出现可逆。退火处理引起S-S键态变化,导致非晶半导体As2S8薄膜结构达到一定稳定状态,伴随着薄膜厚度的减小。As2S8平面波导在130C 温度退火,然饱和光照,又经过130C 温度退火处理后,显示出约为0.27 dB/cm低的传输损耗,在波长632.8 nm导模下有良好的光传输性能。     

Electrical and structural characterization of PLD grown CeO2–HfO2 laminated high-k gate dielectrics

The electrical and physical properties of CeO₂–HfO₂ nanolaminates deposited by pulsed laser deposition (PLD) are investigated. The properties of the nanolaminates are compared with binary CeO₂ and HfO₂ thin films. Layers were deposited using CeO₂ and HfO₂ targets at substrate temperatures between 220 and 620 °C in 10 Pa Ar+H₂ or O₂. In situ post deposition anneal (PDA) was achieved by controlled cooling down to room temperature with . Nanolaminates starting with CeO₂ show lower EOT and leakage compared to layers starting with HfO₂. TEM and XRD analyses showed thickness-dependent crystallinity of the layers, varying from amorphous to highly oriented polycrystalline phase.C–V and I–V measurements were done on the capacitors. Lowest fixed-charge density was found for the nanolaminates deposited at 520 °C. The k values of the nanolaminates extracted by the EOT-physical thickness plots were found to be 141, 48 and 22, for deposition temperatures 420, 520 and 620 °C, respectively. Higher k value for lower deposition temperatures is explained by the thickness dependent morphology of the layers. An with was found for binary HfO₂ layer with 4 nm physical thickness. Lowest leakage current density was for a 4 nm laminate deposited at 420 °C and with a cooling rate of 2 °C/min during PDA.