A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integrators

This paper describes a third-order sigma-delta (/spl Sigma//spl Delta/) modulator that is designed and implemented in 0.18-/spl mu/m CMOS process. In order to increase the dynamic range, this modulator takes advantage of mixed-mode integrators that consist of analog and digital integrators. A calibration technique is applied to the digital integrator to mitigate mismatch between analog and digital paths. It is shown that the presented modulator architecture can achieve a 12-dB better dynamic range than conventional structures with the same oversampling ratio (OSR). The experimental prototype chip achieves a 76-dB dynamic range for a 200-kHz signal bandwidth and a 55-dB dynamic range for a 5-MHz signal bandwidth. It dissipates 4 mW from 1.8-V supply voltages and occupies 0.7-mm/sup 2/ silicon area.     

Integrated stereo /spl Delta//spl Sigma/ class D amplifier

A 2/spl times/40 W class D amplifier chip is realized in 0.6-/spl mu/m BCDMOS technology, integrating two delta-sigma (/spl Delta//spl Sigma/) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.     

A 2.2-mW CMOS bandpass continuous-time multibit /spl Delta/-/spl Sigma/ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications

A delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter featuring 68-dB dynamic range and 64-dB signal-to-noise ratio in a 1-MHz bandwidth centered at an intermediate frequency of 2 MHz with a 48-MHz sample rate is reported. A second-order continuous-time modulator employing 4-bit quantization is used to achieve this performance with 2.2 mW of power consumption from a 1.8-V supply. The modulator including references occupies 0.36 mm/sup 2/ of die area and is implemented in a 0.18-/spl mu/m five-metal single-poly digital CMOS process.     

A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/C from -50/spl deg/C to 120/spl deg/C

A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.     

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.     

Highly linear 2.5-V CMOS /spl Sigma//spl Delta/ modulator for ADSL+

We present a 90-dB spurious-free dynamic range sigma-delta modulator (/spl Sigma//spl Delta/M) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25-/spl mu/m CMOS process with metal-insulator-metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within /spl plusmn/0.85 and /spl plusmn/0.80 LSB/sub 14 b/, respectively. The /spl Sigma//spl Delta/ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the /spl Sigma//spl Delta/ modulator.     

Lossless InAsP-InGaP modulator at 1.3 /spl mu/m for optical conversion of radio signals up to 40 GHz

We report on an InAsP-InGaP electroabsorption modulator at 1.3 /spl mu/m integrated with a semiconductor amplifier. The fiber-to-fiber insertion gain reaches +10 dB. The 50-/spl mu/m-long modulator section exhibits a bandwidth of 36 GHz and a -17-dB extinction ratio with 3-V drive voltage. The integrated amplifier produced an RF-link efficiency of -26 dB at 20 GHz without any external amplification.     

A 14-bit, 10-Msamples/s D/A converter using multibit /spl Sigma//spl Delta/ modulation

A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12. The chip was fabricated in a 0.5-/spl mu/m CMOS technology and operates from a single 2.5-V supply.     

A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass /spl Sigma//spl Delta/ modulator with on-chip switched buffer

A second-order multibit bandpass /spl Sigma//spl Delta/ modulator (BP/spl Sigma//spl Delta/M) used for the digitizing of AM/FM radio broadcasting signals at a 10.7-MHz IF is presented. The BP/spl Sigma//spl Delta/M is realized with switched-capacitor (SC) techniques and operates with a sampling frequency of 37.05 MHz. The input impulse current, required by the SC input branch, is minimized by the use of a switched buffer without deteriorating the overall system performance. The accuracy of the in-band noise shaping is ensured with two self-calibrating control systems. In a 0.18-/spl mu/m CMOS technology, the device die size is 1 mm/sup 2/ and the power consumption is 88 mW. In production, the BP/spl Sigma//spl Delta/M features at least 78-dB dynamic range and 72-dB peak SNR within a 200-kHz bandwidth (FM bandwidth). The intermodulation (IMD) is -65 dBc for two tones at -11 dBFS. The robustness of the aforementioned performance is demonstrated by the fact that it has been realized with the BP/spl Sigma//spl Delta/M embedded in the noisy on-chip environment of a complete mixed-signal FM receiver.     

High-efficiency 1.3 /spl mu/m InAsP-GaInP MQW electroabsorption waveguide modulators for microwave fiber-optic links

High-efficiency electroabsorption waveguide modulators have been designed and fabricated using strain-compensated InAsP-GaInP multiple quantum wells at 1.32-/spl mu/m wavelength. A typical 200-/spl mu/m-long modulator exhibits a fiber-to-fiber optical insertion loss of 9 dB and an optical saturation intensity larger than 10 mW. The 3-dB electrical bandwidth is in excess of 20 GHz with a 50-/spl Omega/ load termination. When used in an analog microwave fiber-optic link without amplification, a RF link efficiency as high as -38 dB is achieved at 10 mW input optical carrier power. These analog link characteristics are the first reported using MQW electroabsorption waveguide modulators at 1.32 /spl mu/m.     

A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth

This paper presents the design and experimental results of a continuous-time /spl Sigma//spl Delta/ modulator for ADSL applications. Multibit nonreturn-to-zero (NRZ) DAC pulse shaping is used to reduce clock jitter sensitivity. The nonzero excess loop delay problem in conventional continuous-time /spl Sigma//spl Delta/ modulators is solved by our proposed architecture. A prototype third-order continuous-time /spl Sigma//spl Delta/ modulator with 5-bit internal quantization was realized in a 0.5-/spl mu/m double-poly triple-metal CMOS technology, with a chip area of 2.4 /spl times/ 2.4 mm/sup 2/. Experimental results show that the modulator achieves 88-dB dynamic range, 84-dB SNR, and 83-dB SNDR over a 1.1-MHz signal bandwidth with an oversampling ratio of 16, while dissipating 62 mW from a 3.3-V supply.     

Bandpass traveling-wave Mach-Zehnder modulator in LiNbO/sub 3/ with domain reversal

A bandpass traveling-wave Mach-Zehnder modulator is demonstrated in a Z-cut LiNbO/sub 3/ substrate where quasi-phase-matching is achieved by using a crystal domain reversal and a simple uniform coplanar waveguide electrode structure. The domain reversal was created, by using electric-field poling, to implement the three-section alternating electrooptic interaction. At the operating wavelength /spl lambda/=1.32 /spl mu/m, the modulator has a 15 GHz-broad bandpass response centered at 25-GHz 3.6-dB fiber-to-fiber insertion loss, 12 V on-off voltage at the center frequency, and -33-dB extinction ratio.     

A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW.<>     

Single-chip per channel codec with filters utilizing /spl Delta/-/spl Sigma/ modulation

A single-chip per channel codec with filters, fabricated using a single poly-Si NMOS technology, is discussed. In the encoder, the analog signal is converted to a 2.048 M samples/s digital signal by a /spl Delta/-/spl Sigma/ modulator. Filtering necessary for the sampling rate 8 k sample/s and compression by the /spl mu/255 law are performed digitally. In the decoder, the 8 k samples/s PCM is successively resampled and converted into the 2.048 M samples/s /spl Delta/-/spl Sigma/ signal, which is then decoded by a /spl Delta/-/spl Sigma/ demodulator. All the high-frequency images, which appear around multiples of 8 kHz, are removed by digital filters. The chip has continuous-signal antialiasing and smoothing filters for the 2.048 Samples/s sampling rate. It also has reference voltage generators for /spl Delta/-/spl Sigma/ modulation/demodulation. Some of the observed characteristics are given. The NMOS /spl Delta/-/spl Sigma/ modulator requires only two on-chip matched capacitors as precision components, and does not require a linear amplifier. A deliberate quantization step imbalance is introduced to allow a low sampling rate. The main band limiting for the 8 k samples/s is done by the recursive filter. This is realized with the serial-parallel pipeline multiplier (SPPM) in four-phase logic. The whole system is integrated on a 296 mil/spl times/342 mil chip.     

Electroabsorption waveguide modulators at 1.3 /spl mu/m fabricated on GaAs substrates

An InGaAs-InAlAs multiple-quantum-well (MQW) electroabsorption (EA) waveguide modulator fabricated on a GaAs substrate has been designed and characterized at 1.3-/spl mu/m wavelength for microwave signal transmission on an analog fibre-optic link. The modulator structure with a lattice constant 2.5% larger than that of GaAs is grown upon a 0.7-/spl mu/m-thick three-stage compositionally step-graded In/sub z/Al/sub 1-z/As relaxed buffer. The waveguide modulator exhibits a high-electrooptic slope efficiency of 0.56 V/sup -1/, a 3-dB electrical bandwidth of 20 GHz, and a large optical saturation intensity in excess of 17 mW. These high-speed optoelectronic modulators could potentially be integrated with on-chip GaAs electronic driver circuits.     

A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.     

A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-/spl mu/m CMOS

A high-resolution multibit sigma-delta analog-to-digital converter (ADC) implemented in a 0.18-/spl mu/m CMOS technology is introduced. The circuit is targeted for an asymmetrical digital subscriber line (ADSL) central-office (CO) application . An area- and power-efficient realization of a second-order single-loop 3-bit modulator with an oversampling ratio of 96 is presented. The /spl Sigma//spl Delta/ modulator features an 85-dB dynamic range over a 300-kHz signal bandwidth. The measured power consumption of the ADC core is only 15 mW. An innovative biasing circuitry is introduced for the switched-capacitor integrators.     

A 1-V 10.7-MHz switched-opamp bandpass /spl Sigma//spl Delta/ modulator using double-sampling finite-gain-compensation technique

A 1 V switched-capacitor (SC) bandpass sigma-delta (/spl Sigma//spl Delta/) modulator is realized using a high-speed switched-opamp (SO) technique with a sampling frequency of up to 50 MHz, which is improved ten times more than prior 1 V SO designs and comparable to the performance of the state-of-the-art SC circuits that operate at much higher supply voltages. On the system level, a fast-settling double-sampling SC biquadratic filter architecture is proposed to achieve high-speed operation. A low-voltage double-sampling finite-gain-compensation technique is employed to realize a high-resolution /spl Sigma//spl Delta/ modulator using only low-DC-gain opamps to maximize the speed and to reduce power dissipation. On the circuit level, a fast-switching methodology is proposed for the design of the switchable opamps to achieve a switching frequency up to 50 MHz. Implemented in a 0.35-/spl mu/m CMOS process (V/sub TP/=0.82 V and V/sub TN/=0.65 V) and at 1 V supply, the modulator achieves a measured peak signal-to-noise-and-distortion ratio (SNDR) of 42.3 dB at 10.7 MHz with a signal bandwidth of 200 kHz, while dissipating 12 mW and occupying a chip area of 1.3 mm/sup 2/.     

A 64-MHz clock-rate /spl Sigma//spl Delta/ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.     

A 0.5-V 1-/spl mu/W successive approximation ADC

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.