Fabrication of low defect density 3C-SiC on SiO2 structures using wafer bonding techniques

This paper reports on a process to fabricate single-crystal 3C-SiC on SiO₂ structures using a wafer bonding technique. The process uses the bonding of two polished polysilicon surfaces as a means to transfer a heteroepitaxial 3C-SiC film grown on a Si wafer to a thermally oxidized Si wafer. Transfer yields of up to 80% for 4 inch diameter 3C-SiC films have been achieved. Homoepitaxial 3C-SiC films grown on the 3C-SiC on SiO₂ structures have a much lower defect density than conventional 3C-SiC on Si films.     

用于MEMS器件芯片级封装的金-硅键合技术研究

MEMS器件大都含有可动的硅结构 ,在器件加工过程中 ,特别是在封装过程中极易受损 ,大大影响器件的成品率。如果能在MEMS器件可动结构完成以后 ,加上一层封盖保护 ,可以显著提高器件的成品率和可靠性。本文提出了一种用于MEMS芯片封盖保护的金 硅键合新结构 ,实验证明此方法简单实用 ,效果良好。该技术与器件制造工艺兼容 ,键合温度低 ,有足够的键合强度 ,不损坏器件结构 ,实现了MEMS器件的芯片级封装。我们已经将此技术成功地应用于射流陀螺的制造工艺中     

采用界面薄层氧化硅的硅片直接键合技术研究

本文研究了采用界面薄层氧化硅的硅片直接键合技术。利用原子力显微镜（AFM）和剪切力测试分别表征表面粗糙度和键合强度随着薄层氧化硅厚度的变化情况。对比了采用热氧化和等离子体增强化学气相沉积法（PECVD）两种方法对晶片粗糙度及键合强度的影响。结果表明采用热氧化和PECVD沉积薄层氧化硅做硅片直接键合,键合强度分别可以达到18MPa和8MPa,键合强度随着薄层界面氧化硅厚度的增加而下降,这对于MEMS器件制备及其他硅片直接键合的应用都具有十分重要的指导意义。     

硅片缺陷自动检测分类方法探究

作为电池发电实际效率的重要影响因素,硅片质量具有重要作用。生产硅片的过程中需要综合考虑多种因素,这是因为硅片生产本身具有一定的缺陷。其中,多晶硅片经常性的缺陷主要是纯度不高以及位错缺陷。单晶硅片当中产生的缺陷主要是漩涡缺陷。出现硅片缺陷可能会造成电池片发电能力受到影响,并降低电池的使用寿命。为此,加强对半导体硅片的自动检测分类方法进行研究具有重要意义。     

Germanium-on-insulator substrates by wafer bonding

Single-crystal Ge-on-insulator (GOI) substrates, made by bonding a hydrogen-implanted Ge substrate to a thermally oxidized, silicon handle wafer, are studied for properties relevant to device fabrication. The stages of the layer transfer process are examined through transmission electron microscopy (TEM) from the initial hydrogen implant through the final Ge film polish. The completed GOI substrate is characterized for film uniformity, surface quality, contamination, stress, defectivity, and thermal robustness using a variety of techniques and found to be acceptable for initial device processing.     

Electrically active defects in shallow pre-amorphisedp + n junctions in silicon

An examination of shallow pre-amorphisedp ⁺ n junctions in silicon has revealed three distinct defect related phenomena determined largely by the annealing temperature and relative location of the junction and the amorphous-crystalline (α-c) boundary. For temperatures below 800‡ C all samples displayed leakage currents of ∼10⁻³ A/cm² irrespective of the amorphising atom (Si⁺, Ge⁺ or Sn⁺). The generation centres responsible were identified to be near mid-gap deep level donors lying beyond the α-c interface. For samples annealed above 800‡ C, the leakage current was determined by the interstitial dislocation loops at the α-c boundary. If these were deeper than the junction, a leakage current density of ∼10⁻⁵ A/cm² resulted. From the growth of these loops during furnace annealing it was concluded that the growth was supported by the influx of recoil implanted silicon interstitials initially positioned beyond the α-c boundary. In the case where the as-implanted junction was deeper than the α-c boundary, annealing above 800° C resulted in a transient enhancement in the boron diffusion coefficient. As with the dislocation loop growth, this was attributed to the presence of the recoil implanted silicon interstitials.     

基于混合电极两步键合工艺的阳极键合研究

提出了一种基于新型混合电极的两步键合工艺。阳极键合工艺是在自行设计的多功能键合系统中完成,分析了不同电极配置对键合时间,键合强度以及键合界面的影响,并详细分析了键合界面和键合强度。借助于新型混合电极结构,能够在15-20min内实现无气泡晶圆级阳极键合,其键合强度高于10MPa。 以上结果表明,该种键合方法有非常好的应用价值,能应用于绝大多数晶圆级MEMS封装。     

Fabrication of monolithic photovoltaic arrays on crystalline silicon by wafer bonding and deep etching techniques

In this work, a novel technology to fabricate small (∼1 cm²) c‐Si photovoltaic mini‐modules is shown. This technology combines two main bulk micro‐machining techniques: fusion (or adhesive) bonding and anisotropic etching of silicon. Due to the fact that the photovoltaic cells are fabricated in the same wafer, it is mandatory to etch the whole substrate to ensure electrical isolation. Once the individual cells are bulk‐isolated they can be connected in series so as to scale up the output voltage of the mini‐array. A handling wafer is required to provide mechanical stability to the device wafer. Adhesive and fusion bonding are used to join the handling and the device wafer. First electrical results, under standard Air Mass 1·5 (AM 1·5) solar spectrum light (100 mW/cm²), using a 9‐cell series connected mini‐module fabricated by fusion bonding, leads to a total open‐circuit voltage of 4·11 V, a short‐circuit current of 2·45 mA, and a maximum delivered power of 3·8 mW for each mini‐module (1·4 cm²). A 16‐cell series‐connected mini‐module fabricated by adhesive bonding and wire bonding, yields an open‐circuit voltage of 7·45 V, a short‐circuit current of 390 µA, and maximum delivered power of 1·8 mW, with 1·1 cm² of mini‐module area. Copyright © 2005 John Wiley & Sons, Ltd.     

InP and Si metal-oxide semiconductor structures fabricated using oxygen plasma assisted wafer bonding

In this paper, InP metal-oxide-semiconductor (MOS) structures are fabricated by transferring thermally grown SiO₂ to InP from oxidized Si wafers using oxygen plasma assisted wafer bonding followed by annealing at either 125°C or at 400°C. Well-defined accumulation and inversion regions in recorded capacitance-voltage (C-V) curves were obtained. The long-term stability was comparable to what has been previously reported. The structures exhibited high breakdown fields, equivalent to thermally grown SiO₂-Si MOS structures. The transferring process was also used to fabricate bonded Si MOS structures.     

Fabrication of ultrathin SOI by SIMOX water bonding (SWB)

Ultrathin silicon-on-insulator (SOI) layers of separation by implantation of oxygen (SIMOX) wafers have been transferred onto thermally oxidized silicon wafers by wafer bonding technology. Due to the technical availability and the complementary nature of SIMOX and wafer bonding approaches, SIMOX wafer bonding (SWB) solves some of the respective major difficulties faced by both SIMOX and wafer bonding for device quality ultrathin SOI mass production: the preparation of adequate buried oxide (including its interfaces) in SIMOX and the uniformly thinning one of the bonded wafers to less than 0.1 μm in wafer bonding. The effect of positive charges in the oxide on bondability of ultrathin SOI films and possible applications of SWB will also be outlined.     

基于湿法表面活化处理的InP/SOI晶片键合技术

为了实现集成硅基光源,研究了基于湿法表面处理的InP/SOI直接键合技术。采用稀释的HF溶液对InP晶片进行表面活化处理,同时采用Piranha溶液对SOI晶片进行表面活化处理,实现了二者的低温直接键合。分别采用刀片嵌入法和划痕测试仪对样品的键合强度进行了定性及定量分析。同时,采用超声波扫描显微镜及扫描电子显微镜对键合界面的缺陷信息及键合截面的微观特性进行了评估。分析结果表明:提出的键合工艺可以获得较好的键合效果。     

键合法制备硅基1.55μm InP-InGaAsP量子阱激光器

在硅基上成功地制备出了1.55μm InP-InGaAsP量子阱激光器.设计并生长了适合于键合的量子阱激光器结构材料,通过直接键合技术,将Si衬底与InP-InGaAsP外延片键合到一起.剥离去掉InP衬底后,在5～6μm的薄膜上制备出20μm条形边发射激光器.室温下,阈值电流160mA(电流密度为2.7kA/cm2),功率可达10mW以上(在约350mA电流下),实现了1.55μm长波长边发射激光器与Si的集成.目前,该结果国际上还未见报道.     

带有Bragg反射镜的谐振腔增强型Si光电探测器

采用电子束蒸发和键合技术，制作了具有高反射率的、表面为薄层单晶Si的分布Bragg反射器。用标准光刻工艺在单晶Si薄层上制作出窄带谐振腔增强型（RCE）金属一半导体一金属（MSM）光电探测器，响应峰值波长分别在836、900、965和1030nm处，其中在900nm处峰值半高宽为18nm。该器件具有波长选择特性，可有效抑制相邻频道间的串扰，而且容易制成集成面阵。     

GaAs/Si晶圆片键合偏差及影响因素研究

针对化合物半导体与Si基晶圆异质集成中的热失配问题,利用有限元分析方法开展GaAs半导体与Si晶片键合匹配偏差及影响因素研究,建立了101.6 mm(4英寸)GaAs/Si晶圆片键合匹配偏差评估的三维仿真模型,研究了不同键合结构和工艺对GaAs/Si晶圆级键合匹配的影响,系统分析了键合温度、键合压力、键合介质厚度及摩擦...     

Heterogeneous silicon integration by ultra-high vacuum wafer bonding

Heterogeneous integration of technologically important materials, such as SiC/Si, GaN/Si, Ge/Si, Si/nano-Si/Si, SiC-on-insulator (SiCOI), and ZrO₂/SiO₂/Si, was successfully made by ultra-high vacuum (UHV) wafer bonding. A unique, UHV bonding unit, especially designed to control interface structure, chemistry, and crystallographic orientation within narrow limits, was used to produce homophase and heterophase planar interfaces. In-situ thin-film-deposition capability in conjunction with the wafer bonding offered even more flexibility for producing integrated artificial structures. Prebonding surface preparation was critically important for the formation of strong bonded interfaces. The substrate-surface morphology was examined by atomic-force microscopy (AFM) prior to bonding. In-situ Auger spectroscopy measurements of surface chemistry were invaluable predictors of bonding behaviors. Plasma processing very effectively cleaned the substrates, achieving a near-perfect interfacial bond at the atomic scale. The integrity of the bonded interfaces was studied in the light of their structural and chemical characteristics analyzed by high-resolution, analytical electron microscopy.     

Temperature and duration effects on microstructure evolution during copper wafer bonding

Interfacial morphologies during Cu wafer bonding at bonding temperatures of 300–400°C for 30 min followed by an optional 30-min or 60-min nitrogen anneal were investigated by means of transmission electron microscopy (TEM). Results showed that increased bonding temperature or increased annealing duration improved the bonding quality. Wafers bonded at 400°C for 30 min followed by nitrogen annealing at 400°C for 30 min, and wafers bonded at 350°C for 30 min followed by nitrogen annealing at 350°C for 60 min achieve the same excellent bonding quality.     

High-quality crystalline layer transfer from a silicon-on-insulator substrate onto a sapphire substrate using wafer bonding

We demonstrate layer transfer of 150 nm of Si from a 200-mm, silicon-on-insulator (SOI) substrate onto a sapphire substrate using low-temperature wafer bonding (T=150°C). The crystalline quality and the thermal stability of the transferred Si layer were characterized by x-ray diffraction (XRD). A broadening of the (004) Si peak is observed only for anneal temperatures T_A≥800°C, indicating some degradation of the crystalline quality of the transferred Si film above these temperatures. The measured electron Hall mobility in the bonded Si layer is comparable to bulk silicon for T_A≤800°C, indicating excellent material quality.     

HgCdTe on Si: Present status and novel buffer layer concepts

We discuss buffer-layer concepts for the synthesis of low defect-density HgCdTe epilayers on Si for both hybrid and monolithically integrated, infrared focal-plane arrays (IRFPAa). The primary technical problems to overcome include the 19% lattice-parameter mismatch between HgCdTe and Si, and the (211)B surface orientation required for molecular-beam epitaxy (MBE), the growth technique of choice for HgCdTe. We provide a general overview of IRFPAs, motivations for realizing HgCdTe on Si, the current state-of-the-art parameters as a baseline, and three novel buffer-layer concepts and technologies based on (1) obedient GeSi films on SiO₂, (2) wafer bonding, and (3) chalcogenides.     

GaN基LED与Si键合技术的研究

采用金属键合技术结合激光剥离技术将GaN基LED从蓝宝石衬底成功转移到Si衬底上。利用X射线光电子谱(XPS)研究不同阻挡层对Au向GaN扩散所起的阻挡作用,确定键合所需的金属过渡层。利用多层金属过渡层,在真空、温度400℃和加压300 N下实现GaN基LED和Si的键合,通过激光剥离技术将蓝宝石衬底从键合结构上剥离下来,形成GaN基LED/金属层/Si结构。用金相显微镜及原子力显微镜(AFM)观察结构的表面形貌,测得表面粗糙度(RMS)为12.1 nm。X射线衍射(XRD)和Raman测试结果表明,衬底转移后,GaN基LED的结构及其晶体质量没有发生明显变化,而且GaN与蓝宝石衬底间的压应力得到了释放,使得Si衬底上GaN基LED的电致发光(EL)波长发生红移现象。