The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.      

Analytical Model of $I$– $V$ Characteristics of Arbitrarily Shallow p-n Junctions

For the first time, an analytical model of arbitrarily shallow p-n junctions is presented. Depending on the junction depth, electrical characteristics of ultrashallow p-n junctions can vary from the characteristics of standard Schottky diodes to standard deep p-n junctions. This model successfully unifies the standard Schottky and p-n diode expressions. In the crossover region, where the shallow doping region can be totally depleted, electrical characteristics phenomenologically substantially different from typical diode characteristics are predicted. These predictions and the accuracy of the presented model are evaluated by comparison with the MEDICI simulations. Furthermore, ultrashallow $hbox{n}^{+}$-p diodes were fabricated, and the anomalous behavior in the crossover regime was experimentally observed.      

A $Q$– $f$ Droop Curve for Facilitating Islanding Detection of Inverter-Based Distributed Generation

This paper presents a new method for islanding detection of distributed generation (DG) inverter that relies on analyzing the reactive power versus frequency (Q-f) characteristic of the DG and the islanded load. The proposed method is based on equipping the DG interface with a Q-f droop curve that forces the DG to lose its stable operation once an islanding condition occurs. A simple passive islanding detection scheme that relies on frequency relays can then be used to detect the moment of islanding. The performance of the proposed method is evaluated under the IEEE 1547 and UL 1741 antiislanding test configuration. The studies reported in this paper are based on time-domain simulations in the power systems computer-aided design (PSCAD)/EMTDC environment. The results show that the proposed technique has negligible nondetection zone and is capable of accurately detecting islanding within the standard permissible detection times. In addition, the technique proves to be robust under multiple-DG operation.     

Eigendecomposition of Images Correlated on $S^{1}$, $S^{2}$, and $SO(3)$ Using Spectral Theory

Eigendecomposition represents one computationally efficient approach for dealing with object detection and pose estimation, as well as other vision-based problems, and has been applied to sets of correlated images for this purpose. The major drawback in using eigendecomposition is the off line computational expense incurred by computing the desired subspace. This off line expense increases drastically as the number of correlated images becomes large (which is the case when doing fully general 3-D pose estimation). Previous work has shown that for data correlated on S ¹ , Fourier analysis can help reduce the computational burden of this off line expense. This paper presents a method for extending this technique to data correlated on S ² as well as SO(3) by sampling the sphere appropriately. An algorithm is then developed for reducing the off line computational burden associated with computing the eigenspace by exploiting the spectral information of this spherical data set using spherical harmonics and Wigner-D functions. Experimental results are presented to compare the proposed algorithm to the true eigendecomposition, as well as assess the computational savings.     

22.7-dB Gain $-$19.7-dBm $ICP_{1{rm dB}}$ UWB CMOS LNA

A fully differential CMOS ultrawideband low-noise amplifier (LNA) is presented. The LNA has been realized in a standard 90-nm CMOS technology and consists of a common-gate stage and two subsequent common-source stages. The common-gate input stage realizes a wideband input impedance matching to the source impedance of the receiver (i.e., the antenna), whereas the two subsequent common-source stages provide a wideband gain by exploiting RLC tanks. The measurements have exhibited a transducer gain of 22.7 dB at 5.2 GHz, a 4.9-GHz-wide B _3dB, an input reflection coefficient lower than -10.5 dB, and an input-referred 1-dB compression point of -19.7 dBm, which are in excellent agreement with the postlayout simulation results, confirming the approach validity and the design robustness.     

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- V t and dual- T _ox assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.     

$C$ -Band Optical 90$^{circ}$ -Hybrids Based on Silicon-on-Insulator 4 $times$ 4 Waveguide Couplers

We demonstrate 4times4 multimode interference couplers in a silicon-on-insulator rib waveguide technology that enable compact integrated fully passive optical 90deg-hybrid devices with operation across the C-band.     

Optimal $ Sigma Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency Synthesis

This paper presents a comparative study of $Sigma Delta$ modulators for use in fractional-$ {N}$ phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.      

Some Optimal Binary and Ternary $t$-EC-AUED Codes

Codes that can correct up to t symmetric errors and detect all unidirectional errors are studied. BOumlinck and van Tilborg gave a bound on the length of binary such codes. A generalization of this bound to arbitrary alphabet size is given. This generalized BOumlinck-van Tilborg bound, combined with constructions, is used to determine some optimal binary and ternary codes for correcting t symmetric errors and detecting all unidirectional errors.     

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

Dual-Gate Graphene FETs With $f_{T}$ of 50 GHz

A dual-gate graphene field-effect transistor is presented, which shows improved radio-frequency (RF) performance by reducing the access resistance using electrostatic doping. With a carrier mobility of 2700 cm²/V · s, a cutoff frequency of 50 GHz is demonstrated in a 350-nm-gate-length device. This f_T value is the highest frequency reported to date for any graphene transistor, and it also exceeds that of Si MOS field-effect transistors at the same gate length, illustrating the potential of graphene for RF applications.     

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

VCSEL Intrinsic Response Extraction Using $T$-Matrix Formalism

We present a new method to remove the parasitics contribution to the vertical-cavity surface-emitting laser (VCSEL) chip response, in order to obtain the intrinsic $S_{21}$ behavior. We demonstrate that the chip can be split into two cascaded subsystems representing the electrical access and the optical cavity, respectively. An equivalent electrical circuit defining the behavior of the electrical access is combined with $T$ -matrix formalism to remove the parasitics contribution from the measured $S_{21}$ response. Results allow us to determine the intrinsic 3-dB bandwidth of the VCSEL.      

High-Q Slow-Wave Coplanar Transmission Lines on 0.35 $mu$m CMOS Process

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 $mu$m CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

$n$ -SIFT: $n$ -Dimensional Scale Invariant Feature Transform

We propose the $n$ -dimensional scale invariant feature transform ( $n$-SIFT) method for extracting and matching salient features from scalar images of arbitrary dimensionality, and compare this method's performance to other related features. The proposed features extend the concepts used for 2-D scalar images in the computer vision SIFT technique for extracting and matching distinctive scale invariant features. We apply the features to images of arbitrary dimensionality through the use of hyperspherical coordinates for gradients and multidimensional histograms to create the feature vectors. We analyze the performance of a fully automated multimodal medical image matching technique based on these features, and successfully apply the technique to determine accurate feature point correspondence between pairs of 3-D MRI images and dynamic $3{rm D} + {rm time}$ CT data.      

Influence of Ho-Doping on the Electromagnetic Field-Dependent $E$–$J$ Characteristics of (Bi,Pb)-2212 Superconductor

The magnetic field (B ) dependence of electric field versus transport current density (E-J characteristics) of Bi_1.6Pb_0.5Sr_2-xHo_xCa_1.1Cu_2.1O_8+delta superconductor was studied for x from 0.000 to 0.200. The behavior of supercurrent flow under magnetic fields in Ho-doped (Bi,Pb)-2212 is explained using thermally activated flux-creep. The n -value and characteristic pinning energy ( U_c) estimated from E-J characteristics show that at applied fields, the flux-lines in Ho-doped samples are in the glass-state. A correlation is observed between n -index and J_c of doped samples. The highly enhanced critical current density (J_c) and n-index in both self- and applied-fields due to Ho-doping is of great scientific and technological significance.     

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Density of States-Based DC $I$– $V$ Model of Amorphous Gallium–Indium–Zinc-Oxide Thin-Film Transistors

The density of states (DOS)-based DC I-V model of an amorphous gallium-indium-zinc oxide (a-GIZO) thin-film transistor (TFT) is proposed and demonstrated with self-consistent methodologies for extracting parameters. By combining the optical charge-pumping technique and the nonlinear relation between the surface potential (phiS) and gate voltage (V _GS), it is verified that the proposed DC model reproduces well both the measured V _GS-dependent mobility and the I _DS-V _GS characteristics. Finally, the extracted DOS parameters are N _TA = 4.4 times 10¹⁷ cm^-3 middot eV^-1, N _DA = 3 times 10¹⁵ cm^-3 middot eV^-1, kT _TA = 0.023 eV, kT _DGA = 1.5 eV, and EO = 1.8 eV, with the formulas of exponential tail states and Gaussian deep states.