北斗导航接收机LNA的设计与仿真

为了实现北斗卫星导航接收机射频前端的研制,根据接收机射频模块系统指标要求,包括增益、噪声系数、灵敏度等关键指标要求,提出一种基于ATF54143的LNA设计方案,采用两级结构,源极传输线负反馈稳定技术,实现输入最佳噪声匹配,输出共轭匹配设计,并用ADS软件进行仿真,得到增益32dB,噪声系数0.45dB,输入驻波比1.5。     

多通道射频接收机测量噪声系数的新方法

噪声系数是多通道射频接收机的一个重要参数。传统的噪声系数测量方法对大噪声系数测量存在不足,且测量时通道间会有噪声干扰。提出一种多通道切换优化测量噪声系数的方法:通过设计1个八选一的射频开关实现信道切换,并引入前置低噪声放大器的控制电路提供冷热噪声源,优化Y因子测量噪声系数的方法,实现对各通道的精确测量。由于接收机前端的相似性,该方法可推广应用到其他的射频接收机。     

软件无线电跳频电台接收机射频前端设计

基于软件无线电的基本要求和发展趋势,提出了一种应用在软件无线电跳频电台中接收机射频前端电路结构,分析了接收机射频前端的总体设计方案,包括前端各部分增益的分配、动态范围的分配、噪声系数及灵敏度的计算,讨论了对器件选择的考虑.实际测试结果表明,该射频前端性能指标满足设计要求.     

微波低噪声放大器的设计与仿真

低噪声放大器在接收系统中能降低系统的噪声和接收机灵敏度,是接收系统的关键部件。文中按照低噪声放大器电路的设计要求,完成了2GHz基站前端射频低噪声放大器的电路设计,并通过ADS仿真软件对电路进行仿真和优化。最终表明,采用本方案设计的LNA增益约为15dB,噪声系数约为1．2dB,性能稳定,完全达到了通信接收机中对LNA指标的要求。     

低噪声和高增益CMOS下变频混频器设计

设计并实现了一个用于GPS接收机射频前端的CMOS下变频混频器.基于对有源混频器的噪声机制的物理理解,电路中采用了噪声消除技术,以减少Gilbert型混频器中开关管的闪烁噪声,并引入一个额外的电感与开关对共源节点的寄生电容谐振,改善整个电路的噪声系数和转换增益等关键性能指标.电路采用TSMC 0.25 μm RF CMOS工艺实现,SSB噪声系数为7 dB,电压转换增益为10.4 dB,输入1 dB压缩点为-22 dBm,且输入阻抗匹配良好,输入反射系数为-17.8 dB.全差分电路在2.5 V供电电压下的功耗为10 mW,可满足GPS接收机射频前端对低噪声、高增益的要求.     

光接收机前端等效输入噪声电流谱密度与噪声系数间的关系

根据光接收机前端等效电路模型,建立了噪声系数与等效输入噪声电流谱密度的关系.提出通过测量光接收机前端电路噪声系数间接获得等效输入噪声电流谱密度的方法.155Mb/s高阻结构光接收机前置放大器的电路仿真与计算验证了推导公式的正确性.最后给出在芯片测试实例.     

接收机噪声系数分析

接收机的主要功能是将天线接收到的由目标反射回来的微弱射频信号进行放大、预选、变频、滤波等处理,使目标反射回来的微弱射频信号变成有足够幅度的视频信号或数字信号,以满足信号处理和数据处理的需要.灵敏度表示接收机接收微弱信号的能力,噪声是影响接收机灵敏度的主要因素.分析了接收机链路中主要器件的增益指标对接收机噪声系数的影响,给带宽宽、低噪声、高灵敏度接收机的设计提供借鉴和参考.     

光接收机前端等效输入噪声电流谱密度与噪声系数间的关系

根据光接收机前端等效电路模型,建立了噪声系数与等效输入噪声电流谱密度的关系.提出通过测量光接收机前端电路噪声系数间接获得等效输入噪声电流谱密度的方法.155Mb/s高阻结构光接收机前置放大器的电路仿真与计算验证了推导公式的正确性.最后给出在芯片测试实例.     

射频接收机整机噪声与增益可预测性设计

针对射频前端接收机,提出了一种可预测整机增益和噪声系数的设计方法。给出了完整设计流程,并用MATLAB实现。相对于传统作法,设计过程得到了大大简化。最后应用该方法给出了一个Ku波段射频前端接收机完整设计实例,证明了其可行性。     

镜像频率抑制度对射频前端噪声系数的影响分析

探讨了镜频抑制度对于射频前端噪声系数的影响,分析计算了一次变频系统中有镜频抑制滤波器和无镜频抑制滤波器两种情况下射频前端输出的噪声功率值,分析表明镜频抑制滤波器在一次变频系统中能够改善系统噪声系数约3 dB;针对二次变频系统射频前端的输出噪声功率,分析计算表明当镜频抑制度达到20 dB 以上时,镜像频率对射频前端输出噪声的影响很小,近乎可以忽略。给出一种Ka频段二次变频射频前端的实例,测试结果与理论分析一致。     

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.     

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

超高频射频识别阅读器的高线性低噪声前端

根据超高频段射频识别的协议要求、结合论文所提出的正交直接变频无线收发机架构,对阅读器接收路径所需的系统噪声系数、输入线性度要求做出分析。给出了同时具有低噪声系数、高线性度特点的三级紧凑式射频前端,该电路能够承受标签背散射机制所引起的大信号带内自阻塞干扰。电路采用IBM 0.18μm CMOS 7RF工艺制作,当从3.3V的电源电压上抽取6.9mA电流时,该射频前端可以获得13dBm的输入线性度与23 dB的最大噪声系数。     

基于GaAs肖特基二极管的330GHz接收前端技术研究

基于GaAs肖特基二极管,设计实现了310~330 GHz的接收机前端.接收机采用330 GHz分谐波混频器作为第一级电路,为降低混频器变频损耗,提高接收机灵敏度,分析讨论了反向并联混频二极管空气桥寄生电感和互感,采用去嵌入阻抗计算方法,提取了二极管的射频、本振和中频端口阻抗,实现了混频器的优化设计,提高了变频损耗仿真精度.接收机的165 GHz本振源由×6×2倍频链实现,其中六倍频采用商用有源器件,二倍频则采用GaAs肖特基二极管实现,其被反向串联安装于悬置线上,实现了偶次平衡式倍频,所设计的倍频链在165 GHz处输出约10 dBm的功率,用以驱动330 GHz接收前端混频器.接收机第二级电路采用中频低噪声放大器,以降低系统总的噪声系数.在310~330 GHz范围内,测得接收机噪声系数小于10.5 dB,在325 GHz处测得最小噪声系数为8.5 dB,系统增益为(31±1)dB.     

A 1.57-GHz RF front-end for triple conversion GPS receiver

A low-power, 1.57 GHz RF front-end for a Global Positioning System (GPS) receiver has been designed in a 1.0 μm BiCMOS technology. It consists of a low noise amplifier with 15 dB of gain, a single balanced mixer with 6.3 mS of conversion g_m, a Colpitts LC local oscillator, and an emitter coupled logic (ECL) divide-by-eight prescaler. This front-end has a single sideband (SSB) noise figure of 8.1 dB and is part of a triple conversion superheterodyne receiver whose IF frequencies are 179, 4.7, and 1.05 MHz. Low power consumption has been achieved, with 10.5 mA at 3 V supply voltage for the front-end, while the complete receiver is expected to draw about 12 mA     

基于90nm CMOS工艺的60GHz射频接收前端电路设计

设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59～64 GHz的微波信号下变频至5～10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5～17.5 dB,双边带噪声因子为6.4～7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。     

RF front-end of direct conversion receiver RFIC for cdma-2000

We report on the front-end of a highly integrated dual-band direct-conversion receiver IC for cdma-2000 mobile handset applications. The RF front-end included a CELL-band low-noise amplifier (LNA), dual-band direct-conversion quadrature I/Q down-converters, and a local-oscillator (LO) signal generation circuit. At 2.7 V, the LNA had a noise figure of 1.2 dB and input third-order intermodulation product (IIP3) of 9 dBm. I/Q down-converters had a noise figure of 4-5 dB and IIP3 of 4-5 dBm and IIP2 of 55 dBm. An on-chip phase-locked loop and external voltage-controlled oscillator generated the LO signal. The receiver RFIC was implemented in a 0.35-/spl mu/m SiGe BiCMOS process and meets or exceeds all cdma-2000 requirements when tested individually or on a handset.     

A 2.4-GHz low-IF receiver for wideband WLAN in 6-μmCMOS-architecture and front-end

This paper presents the 2.4-GHz front-end and the first downconversion section of a fully integrated low-IF receiver. The dual-conversion receiver rejects the image repeatably by 60 dB using integrated polyphase filters without calibration or tuning. The gain of the RF mixer and IF amplifier is switchable to slide the available dynamic range of the following stages based on the conditions of the input signal. The front-end and downconversion sections drain 35 mA on average from a 3.3-V supply. Minimum cascade noise figure is 7.2 dB, and maximum cascade IIP3 is -3.4 dBm     

A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network

In this paper, we present a receiver front-end and a frequency source suitable for wireless sensor network applications, in which power consumption is severely restricted under several milliwatts. For such an extremely low-power receiver, current-reusing and frequency multiplying schemes are proposed for both the RF front-end and frequency source. The proposed front-end achieves a conversion gain of 30.5 dB and a noise figure of 10.2 dB at the 10-MHz intermediate frequency (IF), taking only 500-muA bias current from a 1.0-V supply voltage. The measured phase noise of the fabricated frequency source is -115.83 dBc/Hz at 1 MHz offset from a 2.2-GHz center frequency, taking 840 muA from a 0.7-V supply. The front-end performance is compared with the previously reported low-power front-ends operating in similar frequency ranges