Improved clock buffer with high PSRR for SC circuit applications

Clock feedthrough in SC circuits results in low PSRR figures, incompatible with high-performance signal processing. A high-PSRR CMOS clock buffer is presented here, which blocks this power supply (PS) noise coupling path. The presented circuit is a significant improvement over an earlier circuit proposed by the same author, but having a PSRR of over 40 dB now.<>     

开关电流电路中的时钟馈入效应

本文采用ＭＯＳ开关的集总时变ＲＣ模型，对开关电流（ＳＩ）电路中的时钟馈入效应进行了详细的理论分析，导出了开关电流镜中钟馈电压和钟馈电流的表达式，从而揭示出了钟馈电压／电流与工艺参数、ＭＯＳ器件尺寸、时钟信号幅值及其下降沿斜率等之间的内在关系。用它可对ＳＩ电路中时钟馈入的影响进行快速预测。文中的理论分析与ＳＰＩＣＥ仿真结果相一致。所提供的结果对于设计高精度低功耗ＳＩ电路有应用价值。     

Clock feedthrough compensation with phase slope control in SCcircuits

A clock feedthrough compensation technique for SC circuits is presented. The principle is based on the control of the switch turn-off slope. A single control block can drive a large number of identical SC structures, thus minimising area overhead. Experimental results from an integrated prototype show that the injected charge is reduced by a factor as high as 13     

A clock feedthrough reduction circuit for switched-current systems

A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20%     

Precise CMOS current sample/hold circuits using differential clockfeedthrough attenuation techniques

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-μm CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than ±0.4 μA for the input currents from -550 μA to 550 μA. The acquisition time for a 900-μA step transition to 0.1% settling accuracy is 150 ns. For a 410-μA_p-p input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm² and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits     

A switched capacitor circuit simulator: AWEswit

This paper describes the modeling and simulation of switched capacitor circuits in AWEswit. AWEswit is a mixed signal simulator for switched capacitor circuits. It allows for portions of the circuit to be modeled with digital blocks controlled by an event queue. The remainder of the circuit is modeled in the analog domain. The paper describes the circuit formulations employed by AWEswit, and how they are exploited in modeling the nonidealities associated with switched capacitor circuits. AWEswit employs asymptotic waveform evaluation (AWE) as its core simulation engine. It combines circuit formulations in the charge-voltage and current-voltage regimes. This flexibility in the circuit formulations means that if the circuit is modeled entirely with ideal switches (i.e. no resistors), then it is automatically solved in the charge-voltage regime (like SWITCAP2). However, if portions of the circuit need to be solved in the current-voltage regime, then AWEswit automatically partitions the circuit and solves the different partitions in whichever regime is appropriate, i.e., in the current-voltage regime (using AWE to evaluate circuit response) or in the charge-voltage regime. AWEswit naturally handles the bandwidth limitations associated with switched capacitor circuits. In addition, it models the clock feedthrough and signal-dependent charge dump that characterize MOSFET switches. The simulator is illustrated by example     

Clock-feedthrough compensated sample/hold circuits

A novel circuit technique is presented to eliminate the clock feedthrough effect in a sample/hold circuit. The device requirement is minimal, and thus it is quite useful for CMOS monolithic implementation of precise sampled analogue signal processing circuits. Experimental waveforms are also given to demonstrate its validity     

实现Folded-Cascode放大器快速建立的时钟馈通频率补偿

基于有源开关电容网络二阶系统最小建立时间(MST)理论和阶跃响应分析,提出了一种用于Folded-Cascode放大器的频率补偿新方法,即通过MOS电容引入时钟馈通以调整电路阻尼因子η,使其达到MST状态,从而实现快速建立.研究结果表明,补偿后放大器的建立时间缩短了22.7%;当负载电容从0.5变化至2.5pF,其建立时间从3.62ns近似线性地增长到4.46ns;将采用该补偿方法的放大器应用于可变增益(VGA)系统,当闭环增益变化时,仅需调整MOS电容值仍可实现对应状态下的快速建立.     

Measurement and modeling of charge feedthrough in n-channel MOS analog switches

Charge feedthrough in analog MOS switches has been measured. The dependence of the feedthrough voltage on the input and tub voltages, device dimensions, and load capacitances was characterized. Most importantly, it was observed that the feedthrough voltage decreases linearly with the input voltage. The significance of this observation when considering harmonic distortion in sample-and-hold circuits is discussed. A first-order computer simulation based on the quasi-static small-signal MOSFET capacitances shows good agreement with experimental results.     

Full-wave electromagnetic simulation of millimeter-wave active devices and circuits

This paper discusses the most recent progress in developing effective physics-based models for devices operating at millimeter-wave frequencies. The model is based on coupling dynamic electromagnetic wave solutions with carrier transport models. The potentials of this modeling approach for both device simulation and the global simulation of millimeter-wave circuits are demonstrated. Results comparing the full-wave model developed with conventional electrostatic models are provided through the simulation of different microwave transistors. The ability of the model to detect traveling wave effects, such as phase mismatch between the input and output electrodes of a conventional transistor, and their effects on the device gain are also provided. Results from the simulation of an air-bridged gateMesfet, designed to reduce traveling wave effects in high frequency transistors and solve the problem associated with high gate resistance, are illustrated and discussed. Finally, results showing the ability of this technique to model the nonlinearity and the harmonic distortion are provided through the simulation of an amplifier circuit.     

Compact formulation for exact analysis of nonideal SC circuits

A systematic analysis procedure to obtain closed-form expressions for the z-domain transfer functions of SC circuits with finite GB product op-amps is presented. This method allows exact frequential analysis of a general class of SC circuits, without imposing any restriction in the ratio between GB and clock frequencies.     

±0.9 V switched-capacitor CMOS multiplier with rail-to-railinput

An analogue, fully differential, switched capacitor CMOS multiplier with rail-to-rail input capability is presented, together with simulation results. The multiplier can operate at a clock frequency of 10 MHz when operated from a ±0.9 V power supply. Special attention has been given to the minimisation of clock feedthrough errors and also to achieve a low common mode voltage error at the output. The latter makes the device suitable for use in correlators with large integration periods     

SC amplifier and SC integrator with an accurate gain of 2

A fully differential switched-capacitor (SC) amplifier and integrator with an accurate gain of 2 are proposed. Both circuits are based on a novel capacitor mismatch compensation scheme which uses the same capacitor as the charge sampling and summing element. Therefore, the gain error which is linearly proportional to the capacitor mismatch in conventional SC circuits becomes proportional to the square of the mismatch. In addition, the proposed scheme does not require additional active blocks, and the valid output is generated within two clock cycles.     

电荷耦合器件信号电荷转移的数值模拟

建立了线阵埋沟CCD的器件物理模型和数值模拟方法;运用半导体器件模拟软件MEDICI,数值模拟了CCD信号电荷在三相时序脉冲驱动下动态转移过程;模拟计算了CCD电荷转移效率随信号电荷包大小的变化以及暗电子数随埋沟掺杂浓度大小的变化情况。数值模拟结果与理论分析、实验测试结果吻合较好。     

Simulation for signal charge transfer of charge coupled devices

Physical device models and numerical processing methods are presented to simulate a linear buried channel charge coupled devices (CCDs). The dynamic transfer process of CCD is carried out by a three-phase clock pulse driver. By using the semiconductor device simulation software MEDICI, dynamic transfer pictures of signal charges cells, electron concentration and electrostatic potential are presented. The key parameters of CCD such as charge transfer efficiency (CTE) and dark electrons are numerically simulated. The simulation results agree with the theoretic and experimental results.     

Fast feedthrough logic: a high performance logic family for GaAs

A GaAs dynamic logic family using the feedthrough evaluation concept is presented in this paper. Feedthrough logic (FTL) allows the outputs to be partially generated before the input signals arrive. A modified version of this logic, where the function and its complement are implemented in a differential structure, is also introduced. In an FTL gate, the logic outputs are reset to low during the high phase of the clock and evaluated during the low phase of the clock. Resetting to low alleviates the problems of charge sharing and leakage current associated with the other GaAs dynamic logic families. FTL logic functions can be cascaded in a domino-like fashion without a need for the intervening inverters. We employ this novel concept to design several arithmetic circuits. We compare a 4-bit ripple carry adder in FTL with the other published works in terms of device count, area, delay, clock rate and power consumption. The results demonstrate that FTL is the simplest, the fastest, and consumes least power. In addition, our FTL design compares very well with the standard CMOS technology. FTL gates are fully compatible with direct coupled field-effect transistor logic (DCFL), and therefore, can be included in a DCFL standard cell library for improving cell-based ASIC performance. To match the high-speed of the FTL combinational blocks, we present a single-ended latch for pipelining the FTL blocks. Comparisons with the other published results demonstrate the superior performance of our dynamic latch.     

A Novel Integrated CMOS Switch Circuit for High Precision Sample-and-Hold Technique

A new CMOS switch circuit is proposed for the implementationof high precision sample-and-hold. The switch includes a currentmirror and switching action is controlled by current pulses.This reduces charge injection due to clock feedthrough and thecharge injection is input signal independent, resulting in agreatly improved sample-and-hold accuracy.     

A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients

As technology scales down, more single-event transients (SETs) are expected to occur in combinational circuits and thus contribute to the increase of soft error rate (SER). We propose a systematic analysis method to precisely model the SET latching probability. Due to the decreased critical charge and shortened pipeline stage, the SET duration time is likely to exceed one clock cycle. In previous work, the SET latching probability is modeled as a function of SET pulse width, setup and hold times, and clock period for single-cycle SETs. Our analytical model does not only include new dependent parameters such as SET injection location and starting time, but also precisely categorizes the SET latching probabilities for different parameter ranges. The probability of latching multiple-cycle SETs is specifically analyzed in this work to address the increasing ratio of SET pulse width over clock period. We further propose a method that exploits the boundaries of those dependent parameters to accelerate the SER estimation. Simulation results show that the proposed analysis method achieves up to 97% average accuracy, which is applicable for both single- and multiple-cycle SETs. Our case studies on ISCAS’85 benchmark circuits confirm our analysis on the impact of SET injection location and starting time on the SET latching probability. By exploiting our analytical model, we achieve up to 78% simulation time reduction on the process of SET latching probability and SER estimation, compared with Monte-Carlo simulation.     

A micropower fourth-order elliptical switched-capacitor low-pass filter

A micropower fourth-order elliptical switched-capacitor (SC) low-pass filter for biomedical applications has been designed and measured. The charge transfer error of an SC integrator using a transconductance amplifier is discussed. Also first-order noise and PSRR calculations are performed and compared with the results of simulations and measurements. The measurements show that by careful optimization of the gain bandwidth, slew rate, and gain of the amplifiers, high-performance low-power SC filters can be constructed. The cutoff frequency of the filter is 5 kHz, the ripple in the passband is 0.27 dB, and stopband rejection is 49 dB. The power consumption of the filter is 190 /spl mu/W with /spl plusmn/2.5-V power supplies. The dynamic range of the filter is 75 dB, and the total harmonic distortion over the whole passband range is below 0.25% for a 2-V/SUB pp/ input signal. The PSRR of the filter is above 40 dB at frequencies below 3 kHz.