Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates

This paper presents accurate models for the analysis of fault trees based on stochastic logic. To produce the models, probabilistic analysis of static, dynamic and temporal gates is carried out and the probability models are converted to their equivalent stochastic logic gates. A hardware template is also designed for each stochastic logic gate. In the proposed method, users provide fault rates of basic events and immediately evaluate system reliability. Experimental results show that the proposed method is more accurate than previous methods using the proposed stochastic logic gates for dynamic and temporal fault trees. The formula was validated using the Markov model for exponential failure distribution events. The proposed model is applicable for both exponential and non-exponential distributions.     

FPGA-based Monte Carlo simulation for fault tree analysis

The reliability analysis of critical systems is often performed using fault-tree analysis. Fault trees are analyzed using analytic approaches or Monte Carlo simulation. The usage of the analytic approaches is limited in few models and certain kinds of distributions. In contrast to the analytic approaches, Monte Carlo simulation can be broadly used. However, Monte Carlo simulation is time-consuming because of the intensive computations. This is because an extremely large number of simulated samples may be needed to estimate the reliability parameters at a high level of confidence.In this paper, a tree model, called Time-to-Failure tree, has been presented, which can be used to accelerate the Monte Carlo simulation of fault trees. The time-to-failure tree of a system shows the relationship between the time to failure of the system and the times to failures of its components. Static and dynamic fault trees can be easily transformed into time-to-failure trees. Each time-to-failure tree can be implemented as a pipelined digital circuit, which can be synthesized to a field programmable gate array (FPGA). In this way, Monte Carlo simulation can be significantly accelerated. The performance analysis of the method shows that the speed-up grows with the size of the fault trees. Experimental results for some benchmark fault trees show that this method can be about 471 times faster than software-based Monte Carlo simulation.     

基于等效失效率的动态故障树分析

运用动态故障树对动态系统进行可靠性定量分析,当动态子树规模较大时,直接运用马尔可夫理论的难度较大.在综合运用模块化、等效失效率方法的基础上,提出了一种动态故障树顶事件发生概率的近似算法:首先通过深度优先最左遍历来搜索独立模块;接着,对时间域进行不等距划分,将动态门下的子模块看作"准底事件",利用其在各区间内的等效失效率来逐步求取整个动态故障树顶事件的发生概率.通过对实例的求解,验证了此方法的有效性.     

基于贝叶斯网络的复杂系统动态故障树定量分析方法

动态故障树的贝叶斯网络分析方法存在局部组合爆炸和备件门节点失效时间仅能是指数分布的不足.首先,给出动态故障树转换为离散时间贝叶斯网络的方法,该方法使用一个确定性函数来替代条件概率表,避免了局部组合爆炸.然后,根据备件门的失效机理和对应的贝叶斯网络结构特征,解决了备件节点失效时间仅能是指数分布的限制.最后,提出一种基于动态故障树的贝叶斯网络精确推理算法,基于该算法给出了系统失效分布、组件重要度等概率计算.实验结果表明,该方法能有效地分析和评估安全攸关系统的概率特性.     

Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates

In order to have a high level of confidence in system testing, more accurate fault models are needed. An accurate fault model cannot be attained unless all faults in the transistor-level (low level) are considered. However, these transistor-level faults must be mapped onto gate-level (higher level) so that the efficiency of fault simulation, fault emulation and test pattern generation at the gate-level is not sacrificed. This paper covers the static and dynamic single physical failures at transistor-level for static CMOS primitive gates and shows their effects in the output behavior in terms of gate-level faults. A specific fault pattern is proposed and a general formula to calculate the total number of static faults is concluded from these patterns for each type of gate regardless of its number of inputs. The dynamic nature of the physical faults included in the static fault list is evaluated and their cumulative effect on the timing at the circuit output is examined. A general formula for calculating propagation delay at the output due to resistive shorts and opens is derived and a delay fault pattern with variable defect resistance is provided.     

Real Time Fault Diagnosis with Tests of Uncertain Quality for Multimode Systems and its Application in a Satellite Power System

Dynamic fault diagnosis must consider complex fault situations such as fault evolution, coupling, unreliable tests and so on. Previous dynamic fault diagnostic models and inference algorithms are mainly designed for the steady state systems, which are not suitable for the multimode systems. In this paper, a time varying dynamic model to solve the multimode fault diagnosis problem is proposed. Its structure and formulation are presented. Fault diagnosis based on this model is realized by means of inference calculation given the test result, which is formulated as an optimization problem. A new algorithm to solve this problem is proposed. Simulation experiments on different scenarios are carried out to validate the model and the algorithm. As an example, the case of a satellite electrical power system is studied in detail. Both the simulation result and the application result show that the method proposed in this paper can be used to solve the dynamic fault diagnosis problem for multimode systems considering the complex circumstances such as uncertain tests and system delay.     

GPON系统中基于QoS的动态带宽分配算法的研究

为了实现吉比特无源光网络(GPON)带宽分配的公平性,降低网络的丢包率及传输延时,研究了GPON系统传输汇聚层的帧结构及带宽分配的实现方法,提出了一种新的动态带宽分配(DBA)算法--基于QoS的二层动态带宽分配算法.性能分析与对比表明,这种算法对不同用户和不同等级的业务都具有很好的公平性,并可以降低低等级业务的传输延时.     

A proposed DG-FinFET based SRAM cell design with RadHard capabilities

The radiation induced soft errors have become one of the most important and challenging failure mechanisms in modern electronic devices. This paper proposes a new circuit level hardening technique for reduction of soft error failure rate in DG-FinFET (double gate FinFET) based static random access memory (SRAM). Analysis for 32 nm and 45 nm technology nodes is carried out. It is inferred from the paper that the proposed SRAM cell outperforms over DICE latch in terms of fault tolerance of external data and control lines, power dissipation and fast recovery when exposed to radiation for both the technology nodes. This is primarily due to the addition of extra transistors used to neutralize the effect of single event upset without affecting normal operations. Transistor count increase the area and write delay by 7% and 20% respectively over that of DICE latch. While read delay decreases by 14% for the proposed SRAM cell.     

动态电路的混合时序分析方法

 本文基于四事件周期波形模型,提出了一般动态门、LO-CMOS、NTP动态门和N-C²MOS锁存器正确工作的时序约束.将混合时序分析方法应用于动态电路的延时计算,提出了动态门延时测试波形的生成算法,能有效处理多个输入同时翻转对延时的影响.本文的研究成果已在SpiceTime中实现,并且应用于一个32位动态加法器的设计,取得了良好效果,如果不考虑伪路径的影响,求值延时和预充延时的最大误差分别为3.62%和8.26%.     

FPGA-Based Real-Time Power Converter Failure Diagnosis for Wind Energy Conversion Systems

This paper discusses the design, implementation, experimental validation, and performances of a field-programmable gate array (FPGA)-based real-time power converter failure diagnosis for three-leg fault tolerant converter topologies used in wind energy conversion systems (WECSs). The developed approach minimizes the time interval between the fault occurrence and its diagnosis. We demonstrated the possibility to detect a faulty switch in less than 10 $muhbox{s}$ by using a diagnosis simultaneously based on a “time criterion” and a “voltage criterion.” To attain such a short detection time, an FPGA fully digital implementation is used. The performances of the proposed FPGA-based fault detection method are evaluated for a new fault tolerant back-to-back converter topology suited for WECS with doubly fed induction generator (DFIG). We examine the failure diagnosis method and the response of the WECS when one of the power switches of the fault tolerant back-to-back converter is faulty. The experimental failure diagnosis implementation based on “FPGA in the loop” hardware prototyping verifies the performances of the fault tolerant WECS with DFIG.      

基于码流的软件控制FPGA故障注入系统

基于静态随机存储器的现场可编程逻辑门阵列应用于航天电子系统时,易受到单粒子翻转效应的影响,存储数据会发生损坏。为评估器件和电路在单粒子翻转效应下的可靠性,提出一种基于TCL脚本控制的故障注入系统,可在配置码流层面模拟单粒子翻转效应。介绍了该故障注入系统的实现机制和控制算法,并将该软件控制方法与传统硬件控制方法进行对比分析。设计了一种关键位故障模型,从设计网表中提取关键位的位置信息,缩小了故障注入的码流范围。在Virtex-5开发板XUPV5-LX110T上的故障注入实验表明,该故障注入系统能有效模拟单粒子翻转效应,与传统随机位故障注入相比,关键位故障注入的故障率提高了近5倍。     

Directional core selection approach and dynamic tree reorganization for delay and delay variation multicast routing

Multicast communication constrained by end‐to‐end and interdestination delay variation is known as delay and delay variation–bounded multicast. These constraints are salient for real‐time multicast communications. In this paper, we propose a directional core selection algorithm for core selection and delay variation–bounded multicast tree generation. Another algorithm, based on k‐shortest paths, is proposed to further decrease the interdestination delay variation of the trees generated by directional core selection. We also propose the dynamic version of both algorithms that respond to dynamic join and leave requests to the ongoing multicast session by reorganizing the tree and avoiding session disruption. Simulations show that the proposed algorithms surpass existing algorithms in end‐to‐end delay, interdestination delay variation, execution time, and failure probability.     

Design and comparison of new fault-tolerant majority gate based on quantum-dot cellular automata

Quantum-dot cellular automata (QCA) is increasingly valued by researchers because of its nanoscale size and very low power consumption.However,in the manufacture of nanoscale devices prone to various forms of defects,which will affect the subsequent circuits design.Therefore,fault-tolerant QCA architectures have become a new research direction.The purpose of this paper is to build a novel fault-tolerant three-input majority gate based on normal cells.Compared with the previous structures,the majority gate shows high fault tolerance under single-cell and double-cell omission defects.In order to examine the functionality of the proposed structure,some physical proofs under single cell missing defects are provided.Besides,two new fault-tolerant decoders are constructed based on the proposed majority gate.In order to fully demonstrate the performance of the proposed decoder,the previous decoders were thoroughly compared in terms of fault tolerance,area and delay.The result shows that the proposed design has a good fault tolerance characteristic,while the performance in other aspects is also quite good.     

超深亚微米CMOS工艺参数波动的测量电路

分析了超深亚微米工艺参数波动对电路的影响;采用"放大"的思路设计了简单的用于测量超深亚微米工艺门延迟、动态功耗、静态功耗及其波动的电路,并提出了一种用于测量门延迟波动特性曲线的新型电路,该电路采用较短的反相器链可以得到超深亚微米工艺下门延迟波动特性曲线.电路在90nm CMOS工艺下进行了流片制作,得到了90nm CMOS工艺下的单位门延迟波动特性曲线.测得延迟的波动范围为78.6%,动态功耗的波动范围为94.0%,漏电流功耗的波动范围为19.5倍,其中以漏电流功耗的波动性最为严重.     

基于失效物理的集成电路故障定位方法

超大规模集成电路后道工艺(BEOL)中的失效日益增多,例如多层金属化布线桥连、划伤,栅氧化层的静电放电(ESD)损伤、裂纹等失效模式,由于失效点本身尺寸小加上电路规模大,使得失效分析难度增加。为了能够对故障点进行快速、精确定位,提出了基于失效物理的集成电路故障定位方法。根据CMOS反相器电路的失效模式提出了4种主要故障模型:栅极电平连接至电源(地)、栅极连接的金属化高阻或者开路、氧化层漏电和pn结漏电。结合故障模型产生的光发射显微镜(PEM)和光致电阻变化(OBIRCH)现象的特征形貌和位置特点,进行合理的失效物理假设。结果表明,基于该方法可对通孔缺陷、多层金属化布线损伤以及栅氧化层静电放电损伤失效进行有效的定位,快速缩小失效范围,提高失效分析的成功率。     

基于动态错误图的容错计算机系统可靠性分析(英文)

Dependability analysis is an important step in designing and analyzing safety computer systems and protection systems.Introducing multi-processor and virtual machine increases the system faults' complexity,diversity and dynamic,in particular for software-induced failures,with an impact on the overall dependability.Moreover,it is very different for safety system to operate successfully at any active phase,since there is a huge difference in failure rate between hardware-induced and softwareinduced failures.To handle these difficulties and achieve accurate dependability evaluation,consistently reflecting the construct it measures,a new formalism derived from dynamic fault graphs(DFG) is developed in this paper.DFG exploits the concept of system event as fault state sequences to represent dynamic behaviors,which allows us to execute probabilistic measures at each timestamp when change occurs.The approach automatically combines the reliability analysis with the system dynamics.In this paper,we describe how to use the proposed methodology drives to the overall system dependability analysis through the phases of modeling,structural discovery and probability analysis,which is also discussed using an example of a virtual computing system.     

A new fault current-sensing scheme for fast fault protection of the insulated gate bipolar transistor

A new fault current-sensing scheme employing the floating p-well for fast protection of the insulated gate bipolar transistor (IGBT) from the short-circuit faults is proposed and verified by employing 2D mixed mode simulation, based on the previous experimental results. The proposed floating p-well current-sensing scheme detects not the normal operating current but the fault current of the main IGBT by using the diode connected MOSFET and a resistor, when the short-circuit fault occurs. The diode-connected MOSFET eliminates the degradation of the forward voltage drop, because the floating p-well current does not flow under the normal operating condition due to the threshold voltage of the diode connected MOSFET. The proposed current sensor increases the protection speed without any additional delay time by the external blanking filter.     

基于KVM的虚拟机Post-Copy动态迁移算法稳定性优化

虚拟机动态迁移技术为虚拟化系统的资源调度提供了强有力的支撑,Post-Copy算法作为虚拟机动态迁移的两个核心算法之一,凭借其总体迁移时间稳定与迁移停机时间短的优点,一直是国内外学者研究的热点问题。对虚拟机的故障容错机制、迁移过程中的内存页面传输方式与缺页错误的关联性,以及QEMU-KVM平台源码进行了深入的研究,提出了基于事务同步的故障容错方法以提升Post-Copy迁移算法的稳定性。试验结果表明,提出的虚拟机Post-Copy迁移优化算法,能保证迁移过程中源端虚拟机故障、目标端虚拟机故障以及网络故障的迅速修复,能通过较小的代价解决稳定性问题,所提出的方法有效地提升了Post-Copy迁移算法的稳定性,也为以后的优化研究方向提供了参考。     

基于FPGA实现随机逻辑的混合不确定性故障树分析研究

文中提出一种基于随机逻辑的故障树分析方法,即使用混合故障树分析(HFTA)来兼顾客观不确定性和主观不确定性。该方法将每个故障树逻辑门转换为其对应的随机逻辑模块,然后在现场可编程门阵列(FPGA)中实现。随后在a截集置信度水平等于0的情况下比较常规方法和本文方法的精度和性能。分析结果表明,相较于常规混合不确定性分析方法,文中提出的方法缩短了分析时间。由于与常规混合方法的顶事件概率累积分布函数基本相容,可以认为新方法与常规混合方法的结果精度基本一致。     

基于光纤传感技术的大型船闸人字门形变监测方法研究

为实时了解船闸人字门长期满负荷工作可能带来的结构安全问题,提出了一种基于光纤光栅(FBG)传感技术的人字门结构形变在线监测方法。通过对人字门结构进行建模与仿真,弄清门体整体受力分布情况；根据受力分布情况,在人字门上布置若干光纤光栅倾角传感器,实时动态监测门体各部位倾斜角度；将动态倾角变化量转化为结构形变量,建立门体拱度与各点形变量之间的映射关系。结果表明,光纤光栅倾角传感器具有良好的重复性,能够准确反映闸门开、关运行过程；所监测门体最大受力区域为门底枢止水附近,最大拱度在0.1°以内,最大形变量在7mm以内。