Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier

A novel bitline sensing scheme is proposed for low-voltage DRAM to achieve low power dissipation and compatibility with low-voltage CMOS. One of the major obstacles in low-voltage DRAM is the degradation of data-retention time due to low signal level at the memory cell, which requires power-consuming refresh operations more frequently. This paper proposes an offset-cancellation sense-amplifier scheme (OCSA) that improves data-retention time significantly even at low supply voltage. It also improves die efficiency, because the proposed scheme reduces the number of sense amplifiers by supporting more cells in each sense amplifier. Measurements show that the data-retention time of the proposed scheme at 1.5-V supply voltage is 2.4 times of the conventional scheme at 2.0 V.     

A charge recycle refresh for Gb-scale DRAM's in file applications

A charge recycle refresh for low-power DRAM data-retention, featuring alternative operation of two memory arrays, is proposed, and demonstrated using a 64 kb test chip with 0.25 μm technology. After amplification in one array, the charges in that array are transferred to another array, where they are recycled for half amplification. The data-line current dissipation is only half that of the conventional refresh operation, and the voltage bounce of the power supply line is 60% of the conventional. This scheme is further extended for application to n arrays with 1/n data-line current dissipation. Moreover, the multi-array activation with charge recycle refresh is proposed, in which the same peak current as in the conventional scheme is achieved with a small number of refresh cycles for refreshing all the cells     

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead.Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

A cell transistor scalable DRAM array architecture

Presents a new DRAM array architecture for scaled DRAMs. This scheme suppresses the stress bias for memory cell transistors and enables memory cell transistor scaling. In this scheme, the data "1" and data "0" are written to the memory cell in different timing. First, for all selected cells, data "1" is written by boosting wordline (WL) voltage. Second, after pulling down WL voltage to a lowered value, data "0" is written only for data "0" cells. This scheme reduces stress bias for the cell transistor to half of that of the conventional operation. The time loss for data "1" write is eliminated by parallel processing of data "1" write and sense amplifier activation. This scheme realizes fast cycle time of 50 ns. By adopting the proposed scheme, the gate-oxide thickness of the cell transistor is reduced from 5.5 to 3 nm, and the memory cell size is reduced to 87% in 0.13-μm DRAM generation. Moreover, the application of the oxide-stress relaxation technique to all row-path circuits as well as the proposed scheme enables high-performance DRAM with only a thin gate-oxide transistor     

A new extension method of retention time for memory cell on dynamic random access memory

Demands have been placed on dynamic random access memory (DRAM) to not only increase memory capacity and data transfer speed but also to reduce operating and standby currents. When a system uses DRAM, the restricted data retention time necessitates a refresh operation because each bit of the DRAM is stored as an amount of electrical charge in a storage capacitor. Power consumption for the refresh operation increases in proportion to memory capacity. A new method is proposed to reduce the refresh power consumption dynamically, when full memory capacity is not required, by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation of retention times among memory cells. The proposed method reduces the frequency of disturbance and power consumption by two orders of magnitude. Furthermore, the conversion itself can be realized very simply from the structure of the DRAM array circuit, while maintaining all conventional functions and operations in the full array access mode.     

A 1.6-GByte/s DRAM with flexible mapping redundancy technique andadditional refresh scheme

We implemented 72-Mb direct Rambus DRAM with new memory architecture suitable for multibank. There are two novel schemes: flexible mapping redundancy (FMR) technique and additional refresh scheme. This paper shows that multibank reduces redundancy area efficiency. But with the FMR technique, this 16-bank DRAM realizes the same area efficiency as a single-bank DRAM. In other words, FMR reduces chip area by 13%. This paper also describes that additional refresh scheme reduces data retention power to 1/4. Its area efficiency is about four times better than that of the conventional redundancy approach     

A temperature-insensitive self-recharging circuitry used in DRAMs

This paper presents a practical self-recharging circuitry for DRAMs. The proposed self-recharging circuitry not only reduces the standby power by monitoring the voltage drop caused by the data loss of a memory cell but also adjusts the recharging period of the memory cell that results from leakage currents. The proposed design is insensitive to temperature variations. A 1-Kb DRAM using our design is fabricated by a TSMC 0.35-/spl mu/m 1P4M CMOS process. The physical measurement of the proposed design on silicon verifies the correctness of the proposed circuitry.     

A new cell structure with a spread source/drain (SSD) MOSFET and acylindrical capacitor for 64-Mb DRAM's

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs     

Negative resistance element for a static memory cell based onenhanced surface generation [MOS devices]

A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories     

Optimized redundancy selection based on failure-related yield modelfor 64-Mb DRAM and beyond

An optimized redundancy scheme for 64-Mb dynamic RAM (DRAM) and beyond that is based on a failure-related yield model is described. This model accounts for three-dimensional memory cell structures and individual design rules used in individual sections of the chip. Failure-mode parameters for the model are determined by performing a trial fuse-blowing test on 4-Mb DRAMs. The test employs a memory tester without requiring complicated visual inspections. The dependence of the yield on block division and the number of spare elements for a 64-Mb DRAM are investigated. In the estimation as a redundancy scheme for the 64-Mb DRAM, more than two spare rows and two spare columns in 1-Mb or less subblocks are shown to be necessary     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

Block-decoded sense-amplifier driver for high-speed sensing inDRAM's

Safe sensing of the weak cell signal in DRAMs with low sense signals and fast sensing with low peak currents, both important design demands in 64- and 256-Mb DRAM development, are addressed. A block-decoded sense-amplifier driver concept is proposed. Optimized trigger pulse shapes are formed with local driver circuits to achieve high sensing safety at the beginning of the sensing period as well as fast amplification in the cell block containing the addressed memory cell. The nonaddressed blocks are triggered more slowly to reduce the peak current. Thus, reliable sensing of small initial sense signals is obtained in the shortest possible time, while the total current is kept small. As an example, for a 16-Mb DRAM, the sensing time-and hence the access time-can be reduced by at least 5 ns and is about 50% of the conventional sensing time     

A 1-Mbit BiCMOS DRAM using temperature-compensation circuittechniques

A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V_cc variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs     

A well-synchronized sensing/equalizing method for sub-1.0-Voperating advanced DRAMs

Proposes an advanced DRAM array driving technique which can achieve low-voltage operation, a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel effect, and reduces the leakage current. The sense and restore amplifier and equalizer can operate rapidly under a low-voltage operating condition such as 1.0 V V_CC. Therefore, one can make determining the V _th easy for the satisfaction of the high-speed, the low-power dissipation, and a simple device structure. The well-synchronized sensing and equalizing method is applicable to low-voltage operating DRAMs with capacity of 256 Mbits and more     

Low-power on-chip supply voltage conversion scheme forultrahigh-density DRAMs

In order to achieve 3.3-V 1-Gb DRAM and beyond, a new on-chip supply voltage conversion scheme that converts 3.3-V external supply voltage, V_ext, to lowered 1.5-V internal supply voltage, V_ent, without any power loss within the voltage converter is proposed. This scheme connects two identical DRAM circuits in series between V_ixt and V_ss. By operation of two DRAM circuits with the same clock timing, the voltage between two DRAMs, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAMs. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty     

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25-μm CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 μm². Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm²     

Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes

We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate-drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs.     

A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme

In order to achieve small self-refresh current (ICC/sub 6/), the first 256-Mb SDRAM with an on-chip thermometer in the DRAM industry is implemented with a new self-refresh scheme. In addition, the biased reference line (BRL) sensing scheme improving refresh characteristics is proposed to increase refresh period and reduce ICC/sub 6/. The on-chip thermometer is characterized by a small area of 0.43 mm/sup 2/, low power consumption with less than 1-/spl mu/A average current, and good accuracy of 5.85/spl deg/C in the worst case. Good accuracy is achieved by incorporating many generic design techniques, including offset-free operational amplifiers and the chopping method, and small area is achieved by applying DRAM cell technology to integrating analog-digital converter. A 75% reduction in ICC/sub 6/ at 60/spl deg/C is achieved with on-chip thermometer and BRL sensing scheme improving 30% of refresh characteristic.     

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can operate on a 1.8 V power supply as two separate mobile DDR or SDR DRAMs through each channel with maximum data rate of 333 Mbps/pin because of its exclusive accessibility from each channel to memory arrays. Data exchange between two channels is also possible by sharing one common memory array, and a new control scheme of DRAM for this sharing is proposed. The new control scheme is based on direct addressing mode to achieve compatibility with normal DRAM interface together with fast data transfer speed between two channels.