Design and testing of rapid single flux quantum shift registerswith magnetically coupled readout gates

Experimental superconducting shift registers consisting of on-chip clock generators, clock regeneration and distribution circuits, shift register elements, and readout circuits are designed using rapid single flux quantum logic/memory (RSFQ) gates. A 7-b shift register has been tested to 12 GHz and a 17-b to 21 GHz using external triggering clocks with relative delay measurements. Testing with internal clocks generated from Josephson oscillations shows a potential high-speed operation of 45 GHz for the 7-b and 30 GHz for the 17-b shift registers. Two types of magnetically coupled readout gates are discussed. The chips are fabricated using a Nb/AlO_x/Nb Josephson-junction process at a critical-current density of 1000 A/cm². The power dissipation per bit is 3 μW     

Josephson array oscillator with microstrip resonators for submillimeter wave region

Shunted tunnel junctions with a small parasitic inductance have been developed for improving the operating frequency of Josephson array oscillators. The inductance was minimized by reducing the inductive length to 1 μm and was estimated to be about 40 fH. The analysis of resonant properties for the shunted junctions gave a high resonant frequency up to 1.4 THz. Josephson array oscillators were designed and fabricated to operate at near Nb gap frequency (700 GHz) using 11 shunted Nb/AlOx/Nb tunnel junctions with Nb microstrip resonators. Shapiro steps induced by Josephson oscillation were clearly observed above the Nb gap frequency (up to 830 GHz). By fitting the step height to the simulation result using the RLCSJ model, the output power of the Josephson oscillator to the load resistor was estimated to be about 0.1 μW at 680 GHz.     

RSFQ circuitry realized in a SINIS technology process

We have developed integrated circuits in rapid single flux quantum (RSFQ) impulse logic based on intrinsically shunted tunnel junctions as the active circuit elements. The circuits have been fabricated using superconductor-insulator-normalconductor-insulator-superconductor (SINIS) multilayer technology. The paper presents experimental results of the operation of various RSFQ circuits realized in different designs and layouts. The circuits comprise dc/SFQ and SFQ/dc converters, Josephson transmission lines (JTLs), T-flipflops, and analog key components. Functionality has been proved; the circuits have been found to operate correctly in switching. The circuits investigated have a critical current density of j_C=400 A/cm² and a characteristic voltage of V_C=165 μV, the area of the smallest junction is A=24 μm². The junctions exhibit nearly hysteresis-free current-voltage characteristics (hysteresis: less than 7%), the intra-wafer parameter spread for j_C is below ±8%. The margins of the bias current I_b of the circuits have been experimentally determined and found to be larger than ±24%. At preset, constant values of I_b, the range of a separate bias current I_bsw fed to a switching stage integrated between two segments of JTL's is fully covered by the operation margins which are larger than ±56%     

约瑟夫森阵列振荡器的相位锁定分析

系统地研究了超导亚毫米波阵列振荡器的相位锁定问题。为使超导振荡器达到高工作频率、窄线宽和高稳定的性能，约瑟夫森结与结之间的相位必须相互锁定。相位锁定可以通过结与结之间的耦合电路得以实现。通过对振荡器的各种耦合电路的比较表明，蝴蝶领结天线结构是一个比较适合约瑟夫森振荡器相位锁定的耦合电路。本文提出了一种超导亚毫米波阵列振荡器模型并对其进行了模拟计算与分析，仿真得出了振荡器各项参数值，并给出了相位锁定的条件。     

A series of InGaP/InGaAs HBT oscillators up to D-band

In this paper, the development of a series of fixed-frequency heterojunction bipolar transistor (HBT) oscillators from the W- to D-bands is reported. The oscillators are designed based on feedback theory with a small-signal equivalent circuit. This design method enables the achievement of high-output-power oscillators for the management of the power that is generated at the current source inside the HBT. We use a 1 μm×10 μm single-emitter InGaP/InGaAs HBT as an active device for each oscillator, and 50-Ω coplanar waveguides as transmission lines and resonators. Emitter output topology is adopted to reduce the chip size. The series of oscillators achieve the oscillation frequency of 74.8-146.7 GHz. To our knowledge, the 146.7-GHz fundamental oscillation frequency is the highest oscillation frequency achieved thus far using InGaP/InGaAs HBT technology. The output power of the 146.7-GHz oscillator is -18.4 dBm. The chip size of the oscillator is 731 μm×411 μm     

A fully operational 1 kb variable threshold Josephson RAM

The first fully operational Josephson RAM in LSI level integration is described. The chip is designed as a 4 b× 256-word data RAM unit for a 4 b Josephson computer. A variable-threshold memory cell and the related memory architecture are used. They are so simple in structure that the fabrication can be accomplished using current Josephson junction technology. A directly coupled driver gate for a resistive bit line applies an accurate and stable driving current to the memory cell array. The RAM chip is fabricated with a 3 μm Nb/Al-oxide/Nb junction technology. For obtaining reliable RAM chips, a plasma-enhanced CVD (chemical-vapor-deposited) silicon dioxide layer is introduced for insulation between the ground plane and the base electrode. The thermal uniformity of the wafer is improved during the oxidation process for making a tunnel barrier. Installing this RAM chip together with a Josephson processor permitted the functions of a computer, including a memory access, to be successfully demonstrated. The access time was found to be 500-520 ps by measuring a test chip     

Voltage-controlled oscillators up to 98 GHz in SiGe bipolar technology

In this paper, two fully integrated voltage-controlled oscillators (VCOs) in a 200-GHz f/sub T/ SiGe bipolar technology are presented. The oscillators use on-chip transmission lines at the output for impedance transformation. One oscillator operates up to 98 GHz and achieves a phase noise of -85dBc/Hz at an offset frequency of 1 MHz. It can be tuned from 95.2 to 98.4 GHz and it consumes 12 mA from a single -5-V supply. The second oscillator operates from 80.5 GHz up to 84.8 GHz with a phase noise of -87dBc/Hz at 1-MHz offset frequency. The output power of both circuits is about -6dBm.     

Josephson voltage standard based on single-flux-quantum voltagemultipliers

A Josephson single-flux-quantum voltage/frequency multiplier circuit is proposed as the basic building block for a new generation of voltage standards. The circuit uses magnetic coupling to synchronize a series array of independent junction oscillators to the flux flow in a Josephson transmission line. A cascade of these circuits can multiply an arbitrarily low input frequency up to the frequency limit of the circuit (≃250 GHz) and then add the voltages across approximately 30000 oscillators to generate precise voltages up to 10 V. Because the oscillators can be switched on and off with a bias current, the output voltage is rapidly programmable. A complete design for a voltage standard programmable in 1.2-μV increments to a maximum of 10 V is proposed. Using existing fabrication technology, the circuit would cover a substrate area of about 1 cm² and use 67210 junctions     

基于FDTD的约瑟夫森结与超导传输线协同分析方法

为实现高性能处理器,超导RSFQ（快速单磁通量子）电路被提出.该电路主要由超导约瑟夫森结和超导无源传输线组成,对其建模分析是超导RSFQ电路设计的基础.本文提出了基于FDTD（时域有限差分）的约瑟夫森结与超导传输线的协同分析方法.该方法采用FDTD数值方法求解超导传输线的电报方程.在超导传输线与约瑟夫森结交界处的非线性边界条件上,采用了Newton-Raphson迭代算法.数值结果表明,本文提出的约瑟夫森结和超导传输线的协同分析方法与WRspice仿真软件相比具有相同精度,且运算效率显著提高.     

MOS环振式数字加速度传感器

提出了一种新的环振式数字加速度传感器,它采用做在硅梁上的MOS环形振荡器作为敏感元件,两个反方向变化的环振输出信号通过集成在片内的混频器实现频率相减.该传感器具有准数字输出、灵敏度高、温度系数低以及制作工艺简单等特点.分析了环形振荡器的频率特性,以及环形振荡器的谐振频率和加速度的关系,分析并设计了加速度传感器的环形振荡器电路、混频器电路、物理结构以及制作工艺,并制作了样品,其灵敏度为6 .91k Hz/g.     

Bit error rate experiments in ring-shaped RSFQ circuits

Ring-shaped rapid single flux quantum (RSFQ) circuits composed of segments of Josephson transmission lines (JTLs) and other RSFQ circuits enable permanent SFQ pulse circulation. New ring structures of different designs have been realized which comprise T-flipflop (TFF) and multiplier (MULT) circuits. Reliability in circuit operation has been proven experimentally by a bit error rate BER≅10⁻¹⁶. The fabrication process has been optimized by using PTB-4 μm Nb/Al₂O₃–Al/Nb trilayer technology with externally shunted tunnel junctions of critical current densities of j_c=≅1 kA/cm². Characteristic voltage is V_c=250 μV and Steward–McCumber parameter β_c≤1. A linear dependence of pulse circulation frequency on JTL bias currents has been measured within a bias current interval of 20%.     

Waveguide cavity FET oscillator

A new single-tuned oscillator, applicable to power combining circuits, is described in which a probe antenna is used to provide coupling between an active device and the cavity. It is shown that output power, oscillation frequency and injection locking range of the oscillator can be controlled independently in the circuit design. The experiments with low-power FET oscillators demonstrate output power of 44 mW at 9.2 GHz and DC-RF conversion efficiency of 33.2% from a single-device oscillator and about 100% of power combining efficiency in the case of two- and three-device circuits.     

Millimeter wave phase-locking in distributed Josephson arrays

Voltage tunable oscillators operating at millimeter and submillimeter wavelengths can be designed and fabricated using series arrays of Josephson junctions. The coherent radiation obtained from such oscillators results from the mutual phase-locking of the junction through the high-frequency Josephson current generated in the array. A 40-junction array of Josephson junctions distributed over many wavelengths has been designed, fabricated and tested for operation at 100 GHz. This paper presents the experimental results obtained for this prototype array. A review of the theory for optimizing array design is presented along the implications for power generation at submillimeter wavelengths in future arrays.     

An experimental study of the effects of harmonic loading onmicrowave MESFET oscillators and amplifiers

This paper reports an extensive experimental investigation of the effects of second harmonic loading on the performance of microwave GaAs MESFET oscillators; and strongly driven amplifiers. The measurement system used is an active load system based on six-port techniques. Harmonic load pull measurements were obtained for the NE72084 MESFET; the measurements show how the second harmonic load can influence the power gain and the power added efficiency in strongly driven amplifiers. The device line characterization technique was combined with the harmonic load pull technique; the measurement results illustrate how the output power and the DC to RF conversion efficiency of an oscillator depend on the choice of the second harmonic load. Amplifier and oscillator circuits have been designed using these measurements; the circuits have been constructed and measured. The results validate the experimental approach used and clearly illustrate the importance of properly selecting the second harmonic load in amplifier and oscillator circuits. Significant improvements in gain, output power and efficiency have been achieved by properly selecting the second harmonic load     

Picosecond nodal testing of centimeter-size superconducting Nb microstrip interconnects

We have implemented a low-temperature electro-optic sampling system for non-invasive, nodal testing of superconducting Nb integrated circuits. With submillivolt sensitivity and a subpicosecond temporal response, this system has been used to perform nodal analysis on rapid-single-flux quantum (RSFQ) devices and superconducting microstrip interconnects. Here we demonstrate that by measuring the propagation of 6-ps-wide pulses at various test nodes, we are able to fully characterize a superconducting microstrip waveguide the size of an entire chip. The transmission line was selected not only to perform the first complete characterization of a superconducting microstrip, but also to demonstrate full nodal testing of a foundry-fabricated RSFQ integrated circuit. Finally, our results provided much-needed feedback for improving computer simulations of superconducting digital circuits.     

Some comments on potential and space charge distribution in a symmetrical magnetic diode

A general, simple and systematic method for generating RC harmonic oscillators is proposed. These oscillators, which are classified into fifteen oscillator families, are constructed by cross-cascading easily designed first-order circuits. The method is developed by eighteen examples. Single-resistor controlled oscillators, grounded-capacitor oscillators and two-phase oscillators can be designed. It is also shown that GIC circuits can be obtained from some of these oscillator circuits.     

A Technique for the Design of Microwave Transistor Oscillators (Short Paper)

A technique for the design of microwave transistor oscillators is presented in which measurements made on an experimentally optimized amplifier are used to calculate six basis oscillator circuits which yield maximum power output. The procedure has been experimentally verified by the construction of a silicon bipolar transistor test oscillator at 1 GHz.     

Margins and yield in single flux quantum logic

Simulations are used to optimize the design of simple rapid single flux quantum (RSFQ) logic gates and to determine their margins. Optimizations based on maximizing the smallest (critical) margin result in critical margins in the range of 19-50%. A Monte Carlo approach is used to illustrate the relationship between margins and process yield. Based on single gate simulations, the results show that 1 σ parameter spreads of less than about ±5% will be required to make medium- or large-scale integrated RSFQ logic circuits. A single-bit full adder using five RSFQ gates and a local self-timing network are simulated with discrete components. The full adder used 2000-A/cm² junctions with a specific capacitance of 0.04 pF/μ² and had a logic delay of 87 ps and a worst-case margin of ±19%. A small margin reduction which is not present in the individual gate simulations results from loading     

Miniaturized vortex transitional Josephson memory cell by avertically integrated device structure

We have developed the smallest Josephson nondestructive read-out (NDRO) memory cell, called a vortex transitional (VT) memory cell, for a Josephson high-speed 16-Kbit RAM. Its size is 22×22 μm² , which is only 16% of the size of previously developed VT memory cells used in Josephson 4-Kbit RAM. This is achieved by developing a vertically integrated device structure and refining small-junction technology. The cell consists of Nb/AlO_x/Nb junctions, three Nb wirings, SiO₂, insulators and Mo resistors. The VT memory cells operate properly, with a large operating margin of ±20%     

Stability analysis of self-injection-locked oscillators

This paper addresses the stability analysis of the self-injection-locked oscillators. The analysis is developed for arbitrary self-injection feedback loops and illustrated with the specific case of a simple time-delay cable. It is shown that the output phase stability in self-injection-locked oscillators depends on the feedback loop delay and the types of oscillator circuits, which are represented by equivalent parallel- or series-resonant oscillator models. The self-injection-locked technique can also be used to test the oscillator circuit model when the self-coupling phase is known. The theory is verified by using a self-injection-locked GaAs MESFET oscillator operating at X-band with delay loops.