Short-circuit power driven gate sizing technique for reducing powerdissipation

One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order to reduce overall power dissipation. This technique involves a study of short-circuit power dissipation as a function of input signal slews and output load conditions, to aid in making a judicious choice of drive strengths for various gates in a circuit. The resulting low-power solution does not degrade the original performance and yields a circuit which occupies less silicon area. The technique described here can be incorporated into any power optimization or synthesis tool. Lastly, we present the savings in power and area for a 32-b carry lookahead adder which was designed using the technique described here     

Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits

Two versions of a reconfigurable logic element are developed for use in constructing afield-programmable gate array NULL convention logic (NCL) field-programmable gate array (FPGA): one with extra embedded registration capability, which requires additional area, and one without. Both versions can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and both can utilize embedded registration for gates with three or fewer inputs; however, only the version with the additional embedded registration capability can utilize embedded registration with four-input gates. These two approaches are compared with each other and with an existing approach, showing that both versions developed herein yield a more area efficient NCL circuit implementation, compared to the previous work. The two FPGA logic elements are simulated at the transistor level using the 1.8-V, 180-nm TSMC CMOS process.     

Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing

In this paper we propose a new approach to generate a primary input blocking pattern for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. The primary input blocking technique suppresses transitions of gates in the combinational part during scan by assigning controlling values to one of the gates' inputs. However, simultaneously assigning controlling values to the gates may result in conflicts in the setting of binary values on the primary inputs. Instead of the heuristics based on fanout in other approaches, we use the impact function which is based on transition density to determine the priorities of the gates to be blocked. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches.

Variable Input Delay CMOS Logic for Low Power Design

We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has different delays along various input to output paths within the gate. The delays are accomplished by inserting selectively sized ldquopermanently onrdquo series transistors at the inputs of a logic gate. We demonstrate the use of the variable input delay CMOS gates for a totally glitch-free minimum dynamic power implementations of digital circuits. Applying a linear programming method to the c7552 benchmark circuit and using the gates described in this paper, we obtained a power saving of 58% over an unoptimized design. This power consumption was 18% lower than that for an alternative low power design using conventional CMOS gates. The optimized circuits had the same critical path delays as their original unoptimized versions. Since the overall delay was not allowed to increase, the glitch elimination with conventional gates required insertion of delay buffers on noncritical paths. The use of the variable input delay gates drastically reduced the required number of delay buffers.     

Fast low-power decoders for RAMs

Decoder design involves choosing the optimal circuit style and figuring out their sizing, including adding buffers if necessary. The problem of sizing a simple chain of logic gates has an elegant analytical solution, though there have been no corresponding analytical results until now which include the resistive effects of the interconnect. Using simple RC models, we analyze the problem of optimally sizing the decoder chain with RC interconnect and find the optimum fan-out to be about 4, just as in the case of a simple buffer chain. As in the simple buffer chain, supporting a fan-out of 4 often requires noninteger number of stages in the chain. Nevertheless, this result is used to arrive at a tight lower bound on the delay of a decoder. Two simple heuristics for sizing of real decoder with integer stages are examined. We evaluate a simple technique to reduce power, namely, reducing the sizes of the inputs of the word drivers, while sizing each of the subchains for maximum speed, and find that it provides for an efficient mechanism to trade off speed and power. We then use the RC models to compare different circuit techniques in use today and find that decoders with two input gates for all stages after the predecoder and pulse mode circuit techniques with skewed N to P ratios have the best performance     

Compatible cell connections for multifamily dynamic logic gates

Dynamic logic is an alternative way of making logic circuit cells and numerous techniques have been developed to take advantage of its unique characteristics. Particularly, techniques such as the true-single-phase-clock (TSPC) have been used very successfully for fast and low-power applications. However one cannot synthesize dynamic logic gates with the same ease as static gates. One reason is there are no simple rules to connect the many circuit types of dynamic gates to static gates. This paper addresses the problem of finding connection rules for a given set of gate types. The fundamental cell circuit types for dynamic logic gates are analyzed first together with static logic gates. A common set of principles of operation and connections is then identified and later applied to discover which are the feasible connections between cell circuit types identified.     

一种简易红外通信装置的设计与实现

设计了一种简易数字控制红外通信装置,系统硬件部分由红外发射电路、红外接收电路和中转电路三部分组成。系统以STM32F051C4为控制核心,以红外线为载体,采用PWM调制技术、曼彻斯特编码方式,实现了语音和温度信号的实时传输。在保证系统稳定性的同时,通过采用低功耗器件、有效控制发射脉冲占空比等措施,提高中转节点的效率。系统完成硬件电路和软件程序后,经过实验测试,在输入800Hz的正弦信号,接收装置的输出电压有效值不低于0.4V时,红外光发射电路与红外光接收电路之间的传输距离最大为4m;在减小发射端输入信号的幅度至0V时,接收装置输出的噪声电压小于40mV;电路最大供电电流不超过20mA。     

Fault-tolerant analysis of TMR design with noise-aware logic

Due to the effect of thermal noise, ground bounce and process variations in nanometer process, the behavior of any logical circuit becomes increasingly probabilistic. In this paper, based on the noise model [5] on the input and output nodes of a probabilistic CMOS (PCMOS) gate, the correctness probabilities of four PCMOS primitive gates, NOT, NAND, NOR and XOR, can be firstly computed. Based on the concept of the probabilistic transfer matrices (PTMs) and the corresponding operations on PTMs for the serial and parallel compositions of the components in a well-formed circuit, the correctness probability of the output in a 3-input PCMOS majority circuit in a triple modular redundancy (TMR) design can be further computed. For a given circuit with smaller error, it is well known that a TMR design has good fault-tolerant characterization and the correctness probability of the original output is converged to 1. Under the use of noise-aware logic in a TMR design, it is obvious that the fault-tolerant characterization of a TMR design is degraded and the correctness probability of the original output is not converged to 1. The experimental results show that the improvement region of the correctness probability of the original output will be narrowed due to the noise effect on the gates in a 3-input PCMOS majority circuit.     

嵌入式机载视频输出接口设计

针对视频接口接收视频格式单一的问题,设计了一种多格式视频输入接口的视频编码模块。由于采用CH7024视频编码芯片,所以在接口即可接收RGB565和RGB666格式的视频信号。在Linux环境下,对芯片寄存器和视频格式进行配置,编译芯片驱动程序,通过超级终端下载到芯片中,通过CH7024编码芯片将不同格式的输入信号统一转换成CVBS视频的信号输出,这样可减少电路的硬件设计,并通过对软件的修改来接收不同视频格式的信号。实验结果表明,设计的模块能够适应多种视频格式的信号,且编码后的CVBS视频信号输出距离远,抗干扰性强。     

基于NCV门的量子电路故障的检测与定位研究

为了确保基于NCV门库的量子电路的正确性和有效性,给出了量子电路故障定位树的生成算法和量子电路黑盒检测算法来定位量子电路中的门丢失故障。该故障定位树算法去除约98%的无用输出向量,提取输出表中有效的输入向量以及对应的故障输出向量,逐层生成故障定位树。结合量子电路黑盒检测算法对量子电路进行故障定位时不需要访问输出表就能够有效定位量子电路中的丢失门。对benchmarks部分电路进行实验,结果验证了该算法定位单故障门的有效性。     

A dual differential bilateral current convertor

A simple differential input current convertor technique is described. The circuit offers separate input ports for differential voltage and current inputs, while generating a bilateral current output with minimum offset. High common-mode rejection is achieved without any critical component matching.     

Delay-insensitive gate-level pipelining

Gate-level pipelining (GLP) techniques are developed to design throughput-optimal delay-insensitive digital systems using NULL convention logic (NCL). Pipelined NCL systems consists of combinational, registration, and completion circuits implemented using threshold gates equipped with hysteresis behavior. NCL combinational circuits provide the desired processing behavior between asynchronous registers that regulate wavefront propagation. NCL completion logic detects completed DATA or NULL output sets from each register stage. GLP techniques cascade registration and completion elements to systematically partition a combinational circuit and allow controlled overlapping of input wavefronts. Both full-word and bit-wise completion strategies are applied progressively to select the optimal size grouping of operand and output data bits. To illustrate the methodology, GLP is applied to a case study of a 4-bit×4-bit unsigned multiplier, yielding a speedup of 2.25 over the non-pipelined version, while maintaining delay insensitivity.     

A Normalizing aVLSI Network with Controllable Winner-Take-All Properties

We describe an aVLSI network consisting of a group of excitatory neurons and a global inhibitory neuron. The output of the inhibitory neuron is normalized with respect to the input strengths in a manner that is useful in any system where we wish the output signal to code only the strength of the inputs, and not be dependent on the number of active inputs. The circuitry in each neuron is equivalent to that in Lazzaro's winner-take-all (WTA) circuit [1] with one additional transistor and a voltage reference. As in Lazzaro's circuit, the outputs of the excitatory neurons code for the neuron with the largest input. The novel feature is that multiple winners can be chosen (soft-max). By varying one parameter, the network can operate in a soft-max regime or a WTA regime. We show results from two different fabricated networks.     

Bounds on pseudoexhaustive test lengths

Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (cone-independent) and circuit-specific (cone-dependent) bounds on the minimal length of a test required so that each cone in a circuit is exhaustively tested. For any circuit with five or fewer outputs, and where each output has k or fewer inputs, we show that the circuit can always be pseudoexhaustively tested with just 2^k patterns. We derive a tight upper bound on pseudoexhaustive test length for a given circuit by utilizing the knowledge of the structure of the circuit output cones. Since our circuit-specific bound is sensitive to the ordering of the circuit inputs, we show how the bound can be improved by permuting these inputs     

An optically controllable negative resistance circuit constructed with optocouplers

An optocoupler with a Darlington configuration at the output side can be used as a one port active device with a current-controlled negative resistance by simply connecting the input and output sides in cascade. The author proposes an optically controllable negative-resistance circuit constructed with optocouplers. The breakover voltage and the holding current of the negative-resistance characteristics can be controlled widely with two external light inputs. Hence, the circuit may be applied to optronic functional switching operations. It is demonstrated that an optically controlled relaxation oscillator can be easily constructed using the circuit, and that applications of the relaxation oscillator to a light modulator and an optical Schmitt trigger can be realized by simple circuit configurations.     

Static hazards in combinational threshold logic networks†

The possibility of transitory false outputs in conventional digital logic circuits is well known, such output ‘ spikes ’ being the result of different propagation times through the logic network from inputs to output. The usual solution to such ‘ Static hazards ’ is also well known, being the incorporation of additional gates in the system to cover such input transitions. This paper shows that the application of threshold logic gates to logic synthesis has attractions in very easily eliminating such hazards, in many cases without the need for any additional covering gates in the network.     

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.     

A microwave frequency divider using an inverter ring and transmission gates

In this letter, a divide-by-four frequency divider is presented that uses a CMOS inverter ring interspersed with transmission gates. The presence of the transmission gates prevents the inverter ring from oscillating. The signal to be divided is applied to the control voltage to the transmission gates. The integrated circuit operates at an input frequency of 2.2 GHz and yields an output signal at 0.55 GHz. The power dissipation is 14.4 mW. The IC was fabricated using 0.18 /spl mu/m CMOS technology.     

A novel suppressed-link rectifier-inverter topology with near unity power factor

This work describes a novel method in improving the input current total harmonic distortion (THD) as well as the power factor of a three-phase suppressed-link rectifier-inverter circuit. This proposed method makes use of only three bi-directional low power static switches with a relatively simple gating circuit. This paper illustrates how the proposed method is superior in reducing the input current THD of a rectifier-inverter set to about 5%, which is in line with the requirements of IEEE standard 519-1992. This is accomplished without the use of any filter or complex wave shaping techniques. A delta-modulated (DM) voltage source inverter (VSI) with proportional integrator forms the output stage of the converter. It helps to provide constant volts per hertz operation without the need for additional feedback circuitry and complexity. Moreover, this novel DM technique also helps to provide a smooth transition from the pulse width modulation (PWM) to square wave, hence allowing full utilization of the DC bus voltage.