A CMOS Voltage Comparator with Rail-to-Rail Input-Range

A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 m×221 m in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).     

A Slew Controlled LVDS Output Driver Circuit in 0.18 $mu$m CMOS Technology

This article presents a power-efficient low-voltage differential signaling (LVDS) output driver circuit. The proposed approach helps to reduce the total input capacitance of the LVDS driver circuit and hence relaxes the tradeoffs in designing a low-power pre-driver stage. A slew control technique has also been introduced to reduce the impedance mismatch effect between the output driver circuit and the line. The pre-driver stage shows a total input capacitance of 50 fF and also controls the voltage swing and common-mode voltage at the input of the LVDS driver output stage. This makes the operation at low supply voltages using a conventional 0.18 $muhbox{m}$ CMOS technology feasible. The output driver circuit consumes 4.5 mA while driving an external 100 $Omega $ resistor with an output voltage swing of $V_{OD} = $400 mV, achieving a normalized power dissipation of 3.42 mW/Gbps. The area of the LVDS driver circuit is 0.067 ${hbox{mm}}^{2}$ and the measured output jitter is $sigma _{rms} = $4.5 ps. Measurements show that the proposed LVDS driver can be used at frequencies as high as 2.5 Gbps where the speed will be limited by the load $RC$ time constant.      

APFC低压系统的研究与实现

针对低压微电网、机床照明、教学实验和建筑工地临时居住等低电压应用场景中非线性整流设备造成的谐波污染,文中采用单周期控制对低压APFC系统进行研究.文中详细分析了单周期控制器UCC28180的控制原理,并对主电路和控制电路的参数进行了设计.通过对平均电流环路和电压环路分析,结合低压系统非线性电流环路增益因子M1、电压环路...     

Design and Analysis of Built-In Testers for CMOS Switched-Current Circuits

This paper presents the design and analysis of a built-in tester circuit for MOS switched-current circuits used in low-voltage/low-power mixed-signal circuits/systems. The use of the tester can reduce the test length significantly. The developed tester is comprised of a current comparator, a voltage window comparator, and a digital latch. The current comparator is required to have high-accuracy, low-power consumption, simple structure with small chip area, and moderate speed. Results show that the developed current comparator circuit is developed with a small offset current, 0.1 nA, low power consumption, 20 W, and a layout area of 0.01 mm², where the circuit is simulated with the MOSIS SCN 2 m CMOS process parameters and 2 V supply voltage.     

A 0.8 μm BiCMOS Gate Driver for IGBT Power Switch

This paper discusses the design and implementation of a monolithic gate driver for an Insulated Gate Bipolar Transistor (IGBT). The objective is to implement a high voltage (25 V) monolithic gate driver with a novel protection circuit in a conventional low-voltage (5 V) high-density (0.8 m) BiCMOS process. Extended drain MOS-FETs are used to implement the high-voltage capability in this design.     

A high precision low dropout regulator with nested feedback loops

A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a standard CMOS process. The die area is a . The measurement results show that the total error of the output voltage caused by line and load variations is less than ±3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11 V, while the output current is 165 mA, the output load is and 20 in parallel.     

A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations

This paper presents a current driver with a novel high voltage (HV) switch schematic for the use as a protective switch for recording circuits during the stimulation sequence in neural measurement system. The current driver can source and sink currents of amplitudes up to ±8.2 mA with a HV tolerance from 30 V up to 120 V. The proposed HV switch also tolerates the voltage difference up to 120 V between its terminals. Between stimulation sequences the driver provides the effective isolation of the stimulation electrode from ground and HV supply voltage. The inter pulse current is no more than 60 pA. The chip was fabricated with AMS HV 0.35 \(\mu\)m CMOS technology. For test purposes the complete stimulation system including the proposed chip and the external C8051F410 controller was build. For the proposed system the mismatch between the sourced and sinked current does not exceed 20 \(\mu\)A. The possibility to stimulate with frequencies up to 1 kHz is proven by measurement along with the electrode-tissue model.     

A 3-V CMOS low-distortion class AB line driver suitable for HDSLapplications

A fully differential CMOS line driver for use in high bit-rate digital subscriber line (HDSL) services Is presented. The circuit is fabricated in a single-poly quad metal 0.35-μm process and achieves <-70-dB total harmonic distortion while driving up to ±2.4-V, 200-kHz signals into 30 Ω with a 3-V supply. The circuit features a closed loop gain of 6.0 with minimal input capacitance (<200 fF). The circuit requires less than 20 mA of quiescent current and is capable of delivering dynamic currents as large as 180 mA. The circuit is a multistage amplifier utilizing nested-Miller compensation and an enhanced class AB output stage     

A code-pattern-driven digital background calibration technique for SAR ADCs

The article presents the buck converter for the application on headlights of vehicle with chip-level design. The LED components are used as for lighting source, which near/far lights are controlled with high-current switching circuit in the chip. The level-shift circuit and its current driver is proposed to control the input of high-voltage power MOS. The bypass method is presented to reduce the transient time as load current changes suddenly. The input voltage widely ranges from 8 to 21 V while keeping a stable output voltage with 6 V. The chip current can output from 20 to 1500 mA with excellent regulation. This chip had been implemented with TSMC0.25 µm HV- process, and the size of the circuit layout is about 8.6 mm², where includes power switch and far/near lighting switches. Measurements show that peak efficiency can achieve 86.3%. The power regulation is excellent, where the load regulation is only 0.3%, and the line regulation is only 0.5%.

     

基于薄膜SOI的PDP高压寻址驱动集成电路

基于自主开发的薄膜SOI高低压兼容工艺,研制出一种64位输出的薄膜SOI PDP高压寻址驱动集成电路.测试结果显示,该电路具有80 V驱动电压和20 mA输出电流,电路时钟频率大于40 MHz.     

A Design of a Low-Voltage Current-Mode Fully-Differential Analog CMOS Integrator Using FG-MOSFETs and Its Implementation

In the field of analog signal processing, there is a strong need for low-voltage and low-power integrated circuits. Especially in the mobile communication circuitry, an analog signal processing circuit must be fed by dry batteries of 1–1.5 V. This paper presents a design and implementation of a current-mode fully-differential analog CMOS integrator operable with such a low supply voltage. This integrator is built with a cross-coupled matched pair of 3-input FG(Floating Gate)-MOSFETs, a matched pair of 2-input FG-MOSFETs, and four bias current sources. In this circuit, both a low apparent threshold voltage of FG-MOSFETs and voltage signal summation at the floating gates are effectively utilized to enable the circuit operation with a low supply voltage and to simplify the circuit configuration. The influence of the common-mode signal and noise to the signal processing are minimized by adopting fully-differential structure. The performance of the proposed integrator circuit is predicted by theoretical analysis and by HSPICE simulations. The circuit works as an integrator in the frequency range 4–750 MHz at a 1.5 V supply voltage and dissipates DC power of about 70 W. The proposed circuit was fabricated by a Motorola 1.2 m double-poly CMOS process in the chip fabrication program of VLSI Design and Education Center (VDEC).     

一种无运放低压低功耗CMOS带隙基准电压源的设计

采用无运放电路结构,通过改进反馈环路和调整电阻的方法,设计了一种低电压低功耗的带隙基准电压源.相比传统有运放结构,电路芯片面积更小和具有更低的电流损耗,并且大部分电流损耗都用于产生输出电压.基于CSMC 0.5 μmCMOS工艺对所研制带隙基准电压源进行流片,测试结果表明,当电源电压大于0.85 V时,能够产生稳定的输...     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS

A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low-dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the $gm/gds$ ratio of the current sources can be achieved. A power supply rejection of $>,$22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80$~$ pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.25–5 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7$~$V and a clock frequency of 1.6 GHz.      

Design and implementation of a 0.8 V input, 84% duty cycle, variable frequency step-up converter

A 0.8 V input, 84% duty cycle, variable frequency CMOS DC-DC step-up converter with integrated power switches has been presented in this paper. The converter has the properties of both the current mode and hysteric control mode operations. The inductor charging time of the topology is designed to be inversely proportional to the input voltage and as a result the inductor current disturbance dies out immediately. Hence, no external components and extra I/O pins are required for the compensation of the current loop. The step-up converter has been fabricated with a standard pseudo BiCMOS process. Special MOS device of threshold voltage 0.5 V and start-up circuitries enable the converter to start from a voltage as low as 0.8 V. The real time data show that the converter can boost 0.8 V to as high as 5 V, which makes it suitable for low voltage applications. The efficiency of the chip has been found over 75 % for the entire load range from 10 to 100 mA.     

Low voltage bandgap reference with closed loop curvature compensation

A new low-voltage CMOS bandgap reference (BGR) that achieves high temperature stability is proposed. It feeds back the output voltage to the curvature compensation circuit that constitutes a closed loop circuit to cancel the logarithmic term of voltage VBE. Meanwhile a low voltage amplifier with the 0.5μm low threshold technology is designed for the BGR. A high temperature stability BGR circuit is fabricated in the CSMC 0.5μm CMOS tech-nology. The measured result shows that the BGR can operate down to 1 V, while the temperature coefficient and line regulation are only 9 ppm/℃ and 1.2 mV/V, respectively.     

DC-Coupled Burst-Mode Laser Diode Driver with Automatic Power Control for 1.25Gbit/s PON System

An integrated burst-mode laser diode driver is presented for PON application. The bias current range and modulation current range are 1–75 mA and 5–80 mA respectively. The DC-coupled interface between the driver and the laser diode can tolerate the output transient voltage as low as 0.6v. The novel digital APC loop can stabilize the output average optical power and extinction ratio respectively within ± 0.3 dBm and ± 0.4 dB (−40 to 100^∘C) with less than 0.6 μs initialization time and infinite bias current and modulation current hold time. Moreover, the fast burst response is achieved with burst on/off time less than 5 ns. The chip is implemented in a TSMC 0.35-μm SiGe BiCMOS technology and occupies an area of 1.56 × 1.67 mm² with power consumption of 105 mW from a supply voltage of 2.5 v.     

高精度低噪声基准电压源的设计

利用反向带隙电压原理,采用基于CMOS阈值电压的自偏置共源共栅电流镜技术,设计了一种低压低噪声基准电压源.该电压基准源没有外加滤波电容的情况下,通过双极型晶体管大的输出阻抗特性,实现了更低的噪声输出,提高了输出电压的精度.Hspice仿真结果表明,在0.95V电源电压下,输出基准电压为233.9 mV,温度系数为7.6...     

A 1.8 V 900 $mu$ W 4.5 GHz VCO and Prescaler in 0.18 $mu$m CMOS Using Charge-Recycling Technique

This letter presents a charge-recycling VCO and divider in 0.18 $mu$m CMOS technology. The power consumption of the proposed circuit is significantly reduced by stacking the low-voltage divider on the top of the low-voltage VCO, and hence, the VCO reuses the current from the divider. To enhance the reliability of the proposed circuit under supply voltage variation, transistor sharing and adaptive body-biasing techniques are employed. It allows the proposed circuit to operate down to 1.45 V of supply voltage without degrading the FoM. Experimental results show that the proposed circuit achieves 900 $mu$W of power consumption and ${-}184$ dBc/Hz of FoM at 1.8 V.      

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads