Technology of a new n-channel one-transistor EAROM cell called SIMOS

The structure and technology of a new nonvolatile charge-storage device are described. The stacked-gate injection MOS (SIMOS) device is an n-channel MOS transistor with a control gate stacked on the floating gate. In the programming mode, electrons are accelerated by the channel drift field to energies high enough to overcome the barrier height of the Si-SiO2interface and so injected into the floating gate. On account of the channel-injection mechanism performed in the programming mode, channel lengths of less than 4 µm are required. A combination of this condition with the stacked-gate concept is achieved by a self-aligned technique which defines both polysilicon gates by a single photolithographic procedure. By means of the self-aligned technique, both the one-transistor EPROM cell and the one-transistor EAROM cell can be realized. Basic structures of the two different type one-transistor memory cells are the SIMOS transistor and the SIMOS tetrode, respectively. The technology of these two different SIMOS devices is described in detail and experimental results concerning charge accumulation, charge removal, and charge retention are reported.     

Electrically erasable and reprogrammable read-only memory using the n-channel SIMOS one-transistor cell

The stacked-gate injection MOS transistor (SIMOS) uses a control gate stacked on the floating gate for selection of the cell during reading, programming, and erasure. Programming is achieved by the injection of hot electrons from the channel into the floating gate, resulting in a large upward shift in threshold voltage. In both states, operation is in the enhancement mode. Electrical erasure can be performed by injection of hot holes from an avalanche breakdown at the source-substrate junction and by Fowler-Nordheim electron injection from the floating gate to the source. Because the floating gate can be charged positively during the erasure, part of the channel is not covered by the floating gate, and in this way the enhancement mode of the SIMOS transistor after erasure is guaranteed. In a matrix array, the memory cell consists of the SIMOS transistor only. Decoders, read amplifiers, etc., can be integrated on the same substrate. Erasure can be performed as a block, or word-by-word. Different disturb effects on memory cells during programming and erasure are discussed. The cell area of the SIMOS memory is 850 µm². The photograph of a fully decoded 8192-bit SIMOS memory chip is presented.     

A 2×2 analog memory implemented with a special layoutinjector

Using floating gate MOSFETs, we have designed a 2×2 analog memory, which is expandable to any size array. The reduced programming voltage due to the innovative floating gate MOSFETs enables us to construct the analog memory with a standard double poly n-well process. In addition, a novel programming algorithm is presented. This method will contribute not only to a reduced total programming time, but also to a prolonged lifetime of the memory. The high voltage program/erase pulses are arranged to minimize the disturbance of nonselected cells. The resolution of a memory cell has been found to be 10 mV over a range of 1.25 V to 2 V which is equivalent to the information content of 6 digital cells     

Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

This paper describes the narrow and nonspreading distribution of threshold voltage in metal-oxide-nitride-oxide semiconductor (MONOS) memory cell array with Fowler-Nordheim (F-N) channel write operation and direct/F-N tunneling erase operation as a single transistor structure. We fabricated a 4-Mbit MONOS memory test chip using 0.25-/spl mu/m technology. The gate length of the memory cell was shrunk to 0.18 /spl mu/m. The distribution of threshold voltage for many operations were evaluated. The range of threshold voltage distribution is small, within 0.5 V in 12-14 V for programming and -8.5 to -9 V for erasing. It was also narrow for program/erase cycles up to 10/sup 4/ and after exposure to temperatures of 300/spl deg/C for 17 h and 150/spl deg/C for 304 h. These characteristics of narrow Vth distribution represent advantages of the MONOS memory device both for nonverify operation in program/erase mode and for low supply voltage operation in read mode. Another advantage is that no anomalous leak cell or tail bit is evident in the data retention result, demonstrating high reliability. The MONOS memory device is a promising candidate for use in cheaper and more scalable gate length fabrication processes compared with floating gate for highly reliable embedded applications.     

A two-transistor SIMOS EAROM cell

A new, electrically alterable, nonvolatile memory cell, consisting of a floating gate memory transistor and an access transistor, has been developed using the self-aligned n-channel stacked-gate injection-type MOS (SIMOS) technique. Programming is achieved by two mechanisms: channel injection of hot electrons and field emission. Analysis of experimental data shows that the contribution of the field emission mechanism to programming is significantly high when the memory device operates in the depletion mode. Erase occurs via field emission of electrons from the floating gate through a thin oxide thermally grown on monosilicon to an n/SUP +/-diffusion area placed outside the channel region of the memory transistor. This additional floating gate/n/SUP +/-diffusion overlap is also utilized to increase the programming efficiency by applying a voltage to the n/SUP +/-diffusion terminal in addition to the gate and the drain voltage. This voltage is shown to have a strong influence on the two programming mechanisms. Memory retention compares favorably with that of the most advanced electrically programmable, read-only memory (EPROM) devices. Endurance is limited by charge trapping in the thin erase oxide to approximately 10000 write/erase cycles.     

Optimum design of dual-control gate cell for high-density EEPROM's

A new floating-gate-type cell with a dual-control gate (dc cell) has been developed and the structure optimized to realize high-density EEPROM's. In this new cell, an address selection transistor has been eliminated, thus attaining a single-transistor-per-cell configuration. The address selection is achieved by coincidence of two control gates, which are connected to column or row decoders supplied with an appropriate programming voltage. The stored charge in the floating gate suffers some disturbance by repetition of half-selection mode operation--defined as a state in which one of the control gates is set to high and the other to low during programming. In order to improve the endurance of the cell against half-selection mode operation, a new source biasing method has been introduced. As a result, the endurance has been improved by more than 3 orders of magnitude. A WRITE/ERASE endurance of 10⁵cycles and a data retention capability of more than 10 years have been obtained for the dc cell. The design parameters for a 64K EEPROM chip are also described.     

一种新型高速嵌入式动态随机存储器

基于二维器件模拟工具,研究了一种采用栅控二极管作为写操作单元的新型平面无电容动态随机存储器.该器件由一个n型浮栅MOSFET和一个栅控二极管组成.MOSFET的p型掺杂多晶硅浮栅作为栅控二极管的p型掺杂区,同时也是电荷存储单元.写“0”操作通过正向偏置二极管实现,而写“1”操作通过反向偏置二极管,同时在控制栅上加负电压使栅控二极管工作为隧穿场效应晶体管(Tunneling FET)来实现.由于正向偏置二极管和隧穿晶体管开启时接近1μA/μm的电流密度,实现了高速写操作过程,而且该器件的制造工艺与闪烁存储器和逻辑器件的制造兼容,因此适合在片上系统(SOC)中作为嵌入式动态随机存储器使用.     

Novel Single Polysilicon EEPROM Cell With Dual Work Function Floating Gate

A novel single polysilicon electrically erasable programmable read-only memory cell with dual work function floating-gate (DWFG) structure is presented in this letter. The floating gate of the proposed DWFG cell is doped with p+ on the source side and n+ on the drain side. For DWFG devices, the floating gate on the source side has a higher work function than that on the drain side. The work function difference and the intrinsic doped region at the middle of the floating-gate affect the channel potential distribution and generate a peak lateral electric field inside the channel, improving the channel's hot electron programming characteristics. The experimental results show that the proposed DWFG cell gives faster programming speeds and program operation at lower voltage than conventional cells     

A 16 kbit smart 5 V-only EEPROM with redundancy

This paper describes several circuit techniques used in the design of a 5-V-only 16 Kbit EEPROM. The EEPROM uses a two transistor cell based on Fowler-Nordheim tunneling to a floating polysilicon gate. The EEPROM features 5-V-only operation, a self-timed program cycle with automatic erase before write, address and data latches, and a `ready' line output. These features make the program cycle timing compatible with static RAMs and simplifies the microprocessor interface. A new redundancy technique using EE cells as the programming element is also described.     

An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate

Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process. The memory cell consists of a single transistor with stacked gate structure where the floating gate covers only one part of the channel and is extended to an erase overlap of the source diffusion region off the channel. Programming in typically 100 ms/word is achieved by injection of hot electrons from the short channel (3.5 /spl mu/m) into the floating gate. Electrical block erasure is performed by Fowler-Nordheim emission of electrons from the floating gate. To avoid excessive avalanche breakdown currents during erasure 40 nm-50 nm oxides at the erase overlap and a voltage ramp are used. The memory operates with standard voltages (/spl plusmn/5 V, +12 V), during read, program and erase operation, a single pulsed high voltage (+26 V) for programming, and an erase voltage ramp of +35 V maximum. Typical access time is 250 ns.     

The effect of trench-gate-oxide structure on EPROM device operation

A floating-gate erasable programmable read-only memory (EPROM) cell with a thin trench-gate-oxide (TGO) structure near the drain region was fabricated using electron-beam lithography technology. Several promising advantages were found for the TGO cell. The writing time was measured to be 100 faster than conventional devices of the same dimensions. Two-dimensional (2-D) simulation of the TGO structure indicated that longitudinal and transverse channel electric fields are generated which simultaneously increase the hot-electron population in the channel and the injection efficiency into the floating gate. The devices exhibit high-transconductance, fast programming, good-tolerance to unintentional writing during readout, and potential for flash-erase application     

A side-wall transfer-transistor cell (SWATT cell) for highlyreliable multi-level NAND EEPROMs

A multi-level NAND Flash memory cell, using a new Side-WAll Transfer-Transistor (SWATT) structure, has been developed for a high performance and low bit cost Flash EEPROM. With the SWATT cell, a relatively wide threshold voltage (V_th) distribution of about 1.1 V is sufficient for a 4-level memory cell in contrast to a narrow 0.6 V distribution that is required for a conventional 4-level NAND cell. The key technology that allows this wide V_th distribution is the Transfer Transistor which is located at the side wall of the Shallow Trench Isolation (STI) region and is connected in parallel with the floating gate transistor. During read, the Transfer Transistors of the unselected cells (connected in series with the selected cell) function as pass transistors. So, even if the V_th of the unselected floating gate transistor is higher than the control gate voltage, the unselected cell will be in the ON state. As a result, the V_th distribution of the floating gate transistor can be wider and the programming can be faster because the number of program/verify cycles can be reduced. Furthermore, the SWATT cell results in a very small cell size of 0.57 μm² for a 0.35 μm rule. Thus, the SWATT cell combines a small cell size with a multi-level scheme to realize a very low bit cost. This paper describes the process technology and the device performance of the SWATT cell, which can be used to realize NAND EEPROM's of 512 Mbit and beyond     

A new SONOS memory using source-side injection for programming

We reported a new polysilicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming. For the first time, we demonstrated that source-side injection technique, which is commonly used in floating gate nonvolatile memories for its high programming efficiency, can also be used in a SONOS device for achieving high-speed programming. Erase of the device is achieved by tunneling of electrons through the thin top oxide of the ONO charge storage stack. Since the thin top oxide is grown from the nitride layer, the self-saturated nature of the oxidation allows better thickness control. Endurance characteristics indicates that quality of the thin top grown from nitride is as good as the tunnel oxide grown from the silicon substrate. By increasing the top oxide thickness, it is possible to achieve ten years of retention requirement. The self-aligned sidewall gate structure allows small cell size for high density applications     

A simple EEPROM cell using twin polysilicon thin film transistors

A planar twin polysilicon thin film transistor (TFT) EEPROM cell fabricated with a simple low temperature (⩽600°C) process is demonstrated in this work. The gate electrodes of the two TFT's are connected to form the floating gate of the cell, while the source and drain of the larger TFT are connected to form the control gate. The cell is programmed and erased by Fowler-Nordheim tunneling. The threshold voltage of the cell can be shifted by as much as 8 V after programming. This new EEPROM cell can dramatically reduce the cost of production by reducing manufacturing complexity     

An excellent weight-updating-linearity EEPROM synapse memory cellfor self-learning Neuron-MOS neural networks

A new synapse memory cell employing floating-gate EEPROM technology has been developed which is characterized by an excellent weight-updating linearity under the constant-pulse programming. Such a feature has been realized for the first time by employing a simple self-feedback regime in each cell circuitry. The potential of the floating gate is set to the tunneling electrode by the source follower action of the built-in cell circuitry, thus assuring a constant electric field strength in the tunnel oxide at each programming cycle independent of the stored charge in the floating gate. The synapse cell is composed of only seven transistors and inherits all the advanced features of the original six-transistor cell, such as the standby-power free and dual polarity characteristics. In addition, by optimizing the intra-cell coupling capacitance ratios, the acceleration effect in updating the weight has also been accomplished. All these features make the new synapse cell fully compatible with the hardware learning architecture of the Neuron-MOS neural network. The new synapse cell concept has been verified by experiments using test circuits fabricated by a double-polysilicon CMOS process     

A new and flexible scheme for hot-electron programming ofnonvolatile memory cells

A new hot electron writing scheme for flash EEPROMs is proposed that combines a positive source to bulk voltage and a ramped voltage on the control gate. The scheme exploits the equilibrium between hot electron injection and displacement current at the floating gate electrode in order to achieve a transient regime where the drain current of the cell is virtually constant. The new method allows one to accurately control the threshold voltage and the programming drain current that is essentially determined by the slope of the control gate ramp and can thus be traded off with programming time over a wide range of values. The main features of the new scheme are experimentally demonstrated on up-to-date 0.6 μm stacked gate flash EEPROM devices     

Effects of flash EEPROM floating gate morphology on electricalbehavior of fast programming bits

The effects of Flash EEPROM Floating Gate morphology on the generation and density of fast programming bits on a 2-MBit Flash EEPROM array has been characterized. These fast programming bits exhibit identical subthreshold characteristics similar to that of a normal bit after UV-erase, thus establishing that the initial charge stored on the floating gate of both fast and normal bit is the same. This clearly indicates that the fast programming phenomena result from an interaction of the programming process and the floating gate. An in depth experimentation reveals that the floating gate poly deposition and doping process are crucial for controlling the desired Fowler-Nordheim (FN) tunneling. A correlation is established between the fast bit density observed in the 2-MBit array, the FN tunneling currents, the floating gate deposition and doping processes. The fast programming bit threshold voltage distribution and density can be modulated with the floating gate deposition and doping processes     

Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.     

Output properties of charge-injection devices: Part I—Read on injection

New information concerning the readout of charge-injection device (CID) arrays, used for optical detection, is obtained from the well known Kirchhoff voltage equation for surface potential. Emphasis is placed on those readout modes involving read on injection which have been found useful with infrared-sensitive CID's. The theory obtained relates surface potential, depletion depth, mobile charge in the inversion well, and voltage on the floating gate before, during, and after injection. Previous work which obtained some properties of individual gates with filled or empty inversion wells is extended to pairs of coupled gates and partially filled potential wells. Coupled gates operating in ideal mode and in charge-sharing mode, with either column injection or row injection are included. Additional properties derived are high-frequency differential capacitance, output voltage, readout efficiency and its differential analog, transient response, charge-sharing efficiency, and differential charge-sharing efficiency. Numerical computations are given for representative CID pixels on InSb.     

A degradation mechanism of EEPROM cell operational margins whichremains undetected by conventional quality assurance

We report an electron-discharge mechanism from the floating gate of charged EEPROM cells during the first charging operation after baking (250°C, 24 h). For an ensemble of measured EEPROM tells the discharge occurs statistically with threshold-voltage reductions up to over 1 V. Responsible is Fowler-Nordheim (FN) tunneling through the interpolyoxide at the edge where the control gate wraps over the floating gate. This FN tunneling is normally suppressed by a localized highly stable electrical passivation, which is automatically generated by programming operations. Baking partly destroys this passivation so that subsequent cell charging removes more electrons from the floating gate by FN tunneling via the interpolyoxide than it adds via the tunneling oxide