移相器类进动现象对干涉测量的影响

压电晶体(PZT)光学移相器作为移相干涉仪(PSI)的关键部件，其移相误差直接影响被测波面的相位复原精度。分析了压电晶体移相器在移相过程中导致干涉图旋转的原因——类进动，其本质是移相器在伸长的同时其参考镜端面法线方向绕着伸长方向产生旋转。利用典型的Hariharan五步移相算法。得出了类进动现象所导致的波面相位复原误差计算公式，给出了在测试孔径上的误差分布图。对影响误差大小的主要因素如干涉条纹的宽度、旋转的角度和测试口径等进行了具体分析，由此推导出在移相干涉仪光学调整过程中控制干涉图旋转误差的准则。     

高精度0°～360°步级移相器

本文介绍一种由纯电阻平衡电桥构成的正弦移相器,它能够在0°～360°范围内实现任意移相,其移相精度与信号频率无关.文中导出了任意移相的设计公式和桥臂电阻误差与移相误差的关系;同时,也对移相桥工作条件引入的移相误差进行了分析.     

K波段T/R组件高移相精度的研究

T/R 组件作为有源相控阵雷达中的核心部件,其移相精度决定着雷达的性能好坏。 本文对 K 波段的高频 T/R 组件进行了研究,在单独采用数控移相器移相精度较差不满足项目指标要求的情况下,采用数控移相器和小位移相器相结合的方法,使 T/R 组件的移相精度有了很大的改善.测试结果移相均方根误差 RMS 小于 2.3°,同时各移相态的移相精度保持在 8°以内,大大提高了 T/R 组件的移相精度,保证了系统的扫描精度。     

X波段4位数控移相器MMIC研究

采用0.25μm GaAs FET芯片工艺成功制作了X波段4位数控移相器MMIC,对该数控移相器MMIC集成电路的设计、工艺制作过程做了阐述,并给出了实际测试参数.电路设计采用了高低通滤波器式移相器拓扑,串联FET与并联FET组合的电路方式.结果表明,在7.5～8.7 GHz频段内插入损耗≤7 dB,电压驻波比≤1.8∶1,开关时间≤30 ns,移相精度22.5°±2°,45°±3°,90°±3°,180°±3°,所有状态均方根移相误差≤5,控制电压-5 V或0 V.     

基于线性移相误差的[WT《A》]N步移相算法

移相误差是影响移相干涉术测量精度的主要来源,针对移相器的线性移相误差,文中提出一种新型的移相干涉术算法-N步移相算法。该算法通过最小二乘法估计出移相器做等步移相时的实际移相相位,利用上述估计值代入相位计算公式获得被测物体的相位分布。同时对该算法进行仿真研究,其结果表明,算法能准确地估计移相相位,获得被测物体的精确相位分布,并可实现λ/100的高精度测量,且在测量精度上明显优于其他算法。     

一种精度可调的数字控制移相原理

介绍了一种可编程数字控制的移相原理,通过该原理可以设计一种精度可调的数字控制移相器。该原理主要通过一种倍频器倍频因子可调的方式来实现。文中设计的移相器可以在0~360°中达到任意度数的移相,其精度可以达到1°。并可通过精度控制输入信号,进一步提高精度。最后的仿真波形证实了这种原理的可行性。     

S波段单片集成5位数控移相器

南京电子器件研究所研制出 S波段砷化镓单片五位数控移相器。该单片数控移相器采用南京电子器件研究所 76mm圆片 0 .5 μm离子注入标准工艺制作而成。采用集总元件的高通 /低通网络构成移相网络和 Ga As MESFET作为开关控制器件。该移相器在设计工作频带内 32个移相态具有移相精度高 (均方根误差小于 0 .8°)、输入输出驻波好 ( 1 .4)和较低的插入损耗 ( 6d B)与插损变化 ( <± 0 .5 d B)等优良的电特性。S波段单片集成5位数控移相器     

移相术中相移算法的窗函数整数近似方法分析

用离散傅里叶分析的方法将相移过程描述为频谱域滤波的过程,阐明了相移算法的窗函数整数近似法原理.由于相移的有限性会带来频谱泄露的问题,提出了好的移相算法窗函数应该满足主瓣窄、旁瓣小的观点,并给出了根据窗函数整数近似方法设计任意移相间距和任意移相步数移相算法的流程.选择矩形窗、三角窗、hanning窗和blackman窗生成4种11步移相算法,对振动误差和相移误差的分析验证了旁瓣小的harming窗和blaclonan窗生成的算法对误差的灵敏度要小;冉选择harming窗生成了移相间距为π/2的5,11,15,39,51,76和101步7种移相算法,仿真验证了步数越多主瓣越小,对振动抑制能力越好,但需要更高的微位移器移动精度来获得有效的干涉条纹.在满足干涉条纹质量的前提下,步数多的移相算法对移相误差的抑制能力越好.最后模拟实验环境,验证了算法的性能.     

金属陶瓷贴片封装的S波段六位数控移相器

介绍了一款自主设计采用0.25μm GaAs PHMET开关工艺制作的的S波段六位数控移相器芯片和金属陶瓷表贴管壳内的设计方法和研制结果.该移相器在工作频带2.8～3.6 GHz内64个移相态的移相精度RMS＜1.0°、插入损耗IL＜5 dB、输入输出驻波比VSWR＜1.5、幅度均衡△IL＜0.3 dB、1分贝压缩输入...     

一种采用新型矢量合成方法的9~12G 5bit有源本振移相器

本文提出了一种采用新型矢量合成方法的应用于9~12G的5bit有源本振移相器。提出的新型矢量合成方法降低了对可变增益放大器的精度要求,从而可变增益功能可以通过开关控制一组输入管来实现而不必通过改变输入管的偏置电流,所以避免了存在于正交矢量合成移相器中的线性度波动和漏源电压波动的问题,可以降低应用于本振移相时移相器的误差。本文提出的移相器采用TSMC 0.13um CMOS工艺设计并流片。测试结果表明该移相器能够实现5bit的移相精度。在9~12G范围内,32中移相状态下的平均转换增益为-0.5~7dB。均方根增益误差和均方根相位误差的最大值分别为0.8dB和4度。在1.2V的电源电压下消耗的直流电流为27.7mA.     

A self-calibration concept for establishing the complex measurementability of homodyne network analyzers

A homodyne phase-shifter-controlled double reflectometer is presented. Its ability to make complex measurements of a network depends on a knowledge of the phase-shifter characteristics. This knowledge is established using fully unknown standards merely by exploiting reciprocity. If a system error correction is performed, the data needed for error correction contain enough information to determine the behavior of the phase shifter, and no additional standards are needed. It is shown by simulation that the measurement of the parameters of the device under test is only weakly influenced by errors in the phase-shifter behavior     

Design and modeling of 4-bit slow-wave MEMS phase shifters

A true-time-delay multibit microelectromechanical systems (MEMS) phase-shifter topology based on impedance-matched slow-wave coplanar-waveguide sections on a 500-/spl mu/m-thick quartz substrate is presented. A semilumped model for the unit cell is derived and its equivalent-circuit parameters are extracted from measurement and electromagnetic simulation data. This unit cell model can be cascaded to accurately predict N-section phase-shifter performance. Experimental data for a 4.6-mm-long 4-bit device shows a maximum phase error of 5.5/spl deg/ and S/sub 11/ less than -21 dB from 1 to 50 GHz with worst case S/sub 21/ less than -1.2 dB. In a second design, the slow-wave phase shifter was additionally loaded with MEMS capacitors to result in a phase shift of 257/spl deg//dB at 50 GHz, while keeping S/sub 11/ below -19 dB (with S/sub 21/<-1.9 dB). The beams are actuated using high-resistance SiCr bias lines with typical actuation voltage around 30-45 V.     

A production ready, 6-18-GHz, 5-b phase shifter with integratedCMOS compatible digital interface circuitry

A producible, high-yield, monolithic 6-18-GHz, 5-b phase shifter with integrated standard CMOS compatible digital interface circuitry has been developed for use over the -55 to +90°C temperature range. Differential phase shift is achieved using high-pass and low-pass filter structures. The integrated digital interface circuitry produces complementary outputs that are used to bias the phase-shifter bits. The integration of the digital interface circuitry, made with microwave FETs, reduced the phase-shifter bit control bias lines by a factor of 2. The phase shifter was fabricated at both Raytheon's and Texas Instruments' GaAs foundries in production quantities using a standard microwave process. Complete on-wafer RF tests were performed to screen the phase-shifter circuits and determine electrical yield. The phase shifter has an r.m.s. phase error <10° from 6.5 to 18 GHz, maximum insertion loss of 14 dB, and an r.m.s. amplitude error <0.8 dB over the 6-18-GHz band     

基于蒙特卡罗方法的LED芯片定位系统误差分析

该文根据LED芯片定位系统的特点,构建了从图像坐标系到芯片坐标系的数学模型。检测运动控制、图像处理过程以及标定过程中的误差分布,通过蒙特卡罗分析法估计LED芯片的定位误差,计算了各个测量变量对最终定位误差的敏感度。分析结果表明,绕z轴旋转角度误差为LED芯片定位系统误差的主要来源,图像处理误差以及运动控制误差对系统误差影响较小。因此,通过标定算法补偿绕z轴旋转角度误差是提高LED芯片定位精度的关键。     

大下倾角电调基站天线移相器及馈电网络设计

采用耦合串馈移相器和遗传算法天线赋形技术,设计了一个应用于GSM1800 频段动态范围的基站天线。移相通过串馈形式获得大下倾角所需要的移相量。实验表明,该移相器在整个频段内具有良好的幅度变化和插入损耗,所计的基站天线在大下倾角范围内具有很好的上旁瓣抑制和下倾角精度。     

测地激光陀螺仪的倾斜角误差分析

测地激光陀螺仪是测量地球自转角速度的重要工具,为世界时(universal time,UT1) 解算提供依据。环境变化会影响测地激光陀螺仪光学腔的几何形状,从而影响陀螺仪的测量精度。本文主要针对由测地激光陀螺仪平面倾斜带来的陀螺仪萨格奈克(Sagnac) 频差之误差进行研究,结合基本误差理论、坐标系理论,推导出倾斜对陀螺仪旋转角速度影响的理论模型;利用艾伦方差法(Allan deviation,AD) 分析3个实验室的倾斜数据,并根据分析结果对原始数据作去噪处理;在此基础上使用时间序列法建立倾斜误差补偿模型,将倾斜造成的角速度误差降低一个量级,使输出的Sagnac频差更接近理论值。表明通过构建合理的倾斜误差补偿模型,可以改善陀螺仪输出数据的噪声水平,为陀螺仪进一步优化运行环境及相关数据的处理方法提供参考。     

A low local input 1.9 GHz Si-bipolar quadrature modulator with noadjustment

A 1.9 GHz quadrature modulator with an onchip 90° phase-shifter was fabricated using a silicon bipolar technology. This paper investigates error factors caused by a limiter amplifier. It is found that a gain enhancement technique in a phase-shifter circuit is effective in realizing an adjustment free quadrature modulator; we propose a new high-gain phase shifter circuit for this purpose. This technique employs a current mode interface and an on-chip inductor. An image-rejection ratio of over 45 dBc and a carrier feedthrough of below -40 dBc were attained at -15 dBm local oscillator power. This quadrature modulator operates at 2.7 V supply voltage. The operating frequency ranges from 1.2 GHz to 2.3 GHz. The die size of the quadrature modulator IC is 2.49 mm×2.14 mm     

Effective Phase-Shifter Cost as a Selection Criterion

In order to select a phase shifter for a given application, it is necessary to weigh a number of performance factors such that the device selected will result in the lowest overall system cost. This may be accomplished by defining an effective phase-shifter cost in terms of the initial cost of the phase shifter and driver, and dollar factors resulting from insertion loss, phase error, and quantization level.     

Receiving Phased Antenna Array Based on Injection-Locked Harmonic Self-Oscillating Mixers

A 4 times 1 element receiving phased antenna array is presented with phase-shifter elements based on injection-locked harmonic self-oscillating mixers. Each phase-shifter element provides the double functionality of variable phase-shifter and down-converter. The phase-shifts applied to the input signals coming from the different antenna patch elements can be selected by dc control signals in a continuous range of 450deg. The required dc control voltages are calculated for the different incident angles by means of harmonic balance simulations. The influences of phase-shift and conversion gain errors on the beam-steering frequency performance of the antenna are studied. Also illustrated is how the phase-shifter parameters can be optimized in order to minimize the frequency scanning. A 4 times 1 element receiving phased antenna array, with an input frequency band centered at 11.25 GHz and the output frequency band centered at 1.5 GHz, has been manufactured for the experimental validation of the simulated results. A beam scanning range from -23deg to 23deg has been experimentally obtained.     

一种CORDIC算法的精度分析及其在FFT设计中的应用

针对CORDIC算法的精度问题进行了理论分析，首先研究了CORDIC算法中旋转级数、操作数位宽与精度的关系，并将这一结果实际应用于FFT算法的FPGA设计实现中。经实际验证，这种分析的结果是合理的，可作为设计过程中选取旋转级数和操作数数据位宽的参考。