The effect of O<Subscript>2</Subscript> ambient annealing on the microstructure of Cu(Mg) in the form of a Cu(Mg)/SiO<Subscript>2</Subscript>/Si multilayer

The effect of annealing in an O₂ ambient on Cu(Mg)/SiO₂/Si multilayer films was investigated. As-deposited Cu(Mg)/SiO₂/Si multilayer samples with film thicknesses in the 1,000–3,000 ? range were annealed for 30 min in oxygen ambients at pressures ranging from vacuum to 100 mtorr. The results showed that annealing in an 8-mtorr O₂ ambient significantly decreased the electrical resistivity of a 1,000 ? sample from 10.5 μΩ-cm to 3.7 μΩ-cm. Annealing in the O₂ ambient enhanced Mg diffusion to the surface in comparison to vacuum annealing. Furthermore, O₂ ambient annealing leads to excessive grain growth. However, the effect of O₂ ambient annealing on resistivity is less when the thickness of the film increases.     

Thermal Stability Study of Cu(MoN<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript>) Seed Layer on Barrierless Si

This study reports the good thermal stability of a sputtered Cu(MoN _x ) seed layer on a barrierless Si substrate. A Cu film with a small amount of MoN _x was deposited by reactive co-sputtering of Cu and Mo in an Ar/N₂ gas mixture. After annealing at 560°C for 1 h, no copper silicide formation was observed at the interface of Cu and Si. Leakage current and resistivity evaluations reveal the good thermal reliability of Cu with a dilute amount of MoN _x at temperatures up to 560°C, suggesting its potential application in advanced barrierless metallization. The thermal performance of Cu(MoN _x ) as a seed layer was evaluated when pure Cu is deposited on top. X-ray diffraction, focused ion beam microscopy, and transmission electron microscopy results confirm the presence of an ∼10-nm-thick reaction layer formed at the seed layer/Si interface after annealing at 630°C for 1 h. Although the exact composition and structure of this reaction layer could not be unambiguously identified due to trace amounts of Mo and N, this reaction layer protects Cu from a detrimental reaction with Si. The Cu(MoN _x ) seed layer is thus considered to act as a diffusion buffer with stability up to 630°C for the barrierless Si scheme. An electrical resistivity of 2.5 μΩ cm was obtained for the Cu/Cu(MoN _x ) scheme after annealing at 630°C.     

Enhancement of the Stability of Ti and Ni Ohmic Contacts to 4H-SiC with a Stable Protective Coating for Harsh Environment Applications

We report on wafer-level measurements of the long-term stability of Ti and Ni ohmic contacts to n-4H-SiC during thermal treatments in air or air/moisture environments up to 500°C. Contact metallizations with and without a sputtered Ti (20 nm)/TaSi _x (200 nm)/Pt (150 nm) diffusion barrier stack and Ti (20 nm)/TiN (10 nm)/Pt (150 nm)/Ti (20 nm) interconnects were compared. A protective coating consisting of a SiO _x (250 nm)/SiN _y (250 nm) stack deposited by plasma-enhanced chemical vapor deposition (PECVD) was used. The stability of the contact metallizations during long-term thermal treatments in air and air/moisture was studied. The best performance was achieved with Ti ohmic contacts without the Ti/TaSi _x /Pt stack. This system successfully withstood 1000 h thermal treatment at 500°C in air followed by 1000 h at 500°C in air/10% moisture. After the aging, the contact failure ratio was below 1% and the specific contact resistivity amounted to (2.5 ± 1.1) × 10⁻⁴ Ω cm². Scanning electron microscopy (SEM) cross-sectional analysis indicated no degradation in the contact metallization, demonstrating the effectiveness of the SiO _x /SiN _y protective coating in preventing oxidation of the contacts. These results are very promising for applications in harsh environments, where the stability of ohmic contacts is crucial.     

Microstructure control of copper films by the addition of molybdenum in an advanced metallization process

The effect of annealing on the resistivity, morphology, microstructure, and diffusion characteristics of Cu(Mo)/SiO₂/Si and Ti/Cu(Mo)/SiO₂/Si multilayer films has been investigated in order to deterine the role of Mo. In the case of a Cu(Mo)/SiO₂/Si multilayer, most of the Mo diffused out to the free surface to form MoO₃ at temperatures up to 500 C, and complete dissociation of Mo occurred at higher temperatures. The segregation of Mo to the external surface leads to Mo-free Cu films with extensive grain growth up to 20 times the original grain size and strong (111) texture. In the case of a Ti/Cu(Mo)/SiO₂/Si multilayer, a thin Ti film prohibits Cu agglomeration, out-diffusion of Mo, and diffusion of Cu into SiO₂ at temperatures up to 750 C. Cu(Mo) grain growth was less extensive, but (111) fiber texturing was much stronger than in the case of Cu(Mo)/SiO₂/Si. In the current study, significant changes in microstructure, such as a strong (111) texture and abnormal grain growth, have been obtained by adding Mo to Cu films when the films are annealed.     

Effect of Annealing Ambient on the Self-Formation Mechanism of Diffusion Barrier Layers Used in Cu(Ti) Interconnects

Copper (titanium) [Cu(Ti)] films with low titanium (Ti) concentration were found to form thin Ti-rich barrier layers at the film/substrate interfaces after annealing, which is referred to as self-formation of the barrier layers. This Cu(Ti) alloy was one of the best candidates for interconnect materials used in next-generation ultra-large-scale integrated (ULSI) devices that require both very thin barrier layers and low-resistance interconnects. In the present paper, in order to investigate the influences of annealing ambient on resistivity and microstructure of the Cu alloys, the Cu(7.3at.%Ti) films were prepared on the SiO₂ substrates and annealed at 500°C in ultra-high vacuum (UHV) or argon (Ar) with a small amount of impurity oxygen. After annealing the film at 500°C in UHV, the resistivity was not reduced below 16 μΩ-cm. Intermetallic compounds of Cu₄Ti were observed to form in the films and believed to cause the high resistivity. However, after subsequently annealing in Ar, these compounds were found to decompose to form surface TiO _x and interfacial barrier layers, and the resistivity was reduced to 3.0 μΩ-cm. The present experiment suggested that oxygen reactive to titanium during annealing played an important role for both self-formation of the interfacial barrier layers and reduction of the interconnect resistivity.     

Effect of Rapid Thermal Annealing on Sputtered CaCu<Subscript>3</Subscript>Ti<Subscript>4</Subscript>O<Subscript>12</Subscript> Thin Films

Calcium copper titanium oxide (CaCu₃Ti₄O₁₂, abbreviated to CCTO) films were deposited on Pt/Ti/SiO₂/Si substrates at room temperature (RT) by radiofrequency magnetron sputtering. As-deposited CCTO films were treated by rapid thermal annealing (RTA) at various temperatures and in various atmospheres. X-ray diffraction patterns and scanning electron microscope (SEM) images demonstrated that the crystalline structures and surface morphologies of CCTO thin films were sensitive to the annealing temperature and ambient atmosphere. Polycrystalline CCTO films could be obtained when the annealing temperature was 700°C in air, and the grain size increased signifi- cantly with annealing in O₂. The 0.8-μm CCTO thin film that was deposited at RT for 2 h and then annealed at 700°C in O₂ exhibited a high dielectric constant (ε′) of 410, a dielectric loss (tan δ) of 0.17 (at 10 kHz), and a leakage current density (J) of 1.28 × 10⁻⁵ A/cm² (at 25 kV/cm).     

Inkjet printed metallizations for Cu(In1−x Ga x )Se2 photovoltaic cells

This study reports the inkjet printing of Ag front contacts on Aluminum doped Zinc Oxide (AZO)/intrinsic Zinc Oxide (i‐ZnO)/CdS/Cu(In_1−xGa_x)Se₂ (CIGS)/Mo thin film photovoltaic cells. The printed Ag contacts are being developed to replace the currently employed evaporated Ni/Al bi‐layer contacts. Inkjet deposition conditions were optimized to reduce line resistivity and reduce contact resistance to the Al:ZnO layer. Ag lines printed at a substrate temperature of 200°C showed a line resistivity of 2.06 µΩ · cm and a contact resistance to Al:ZnO of 8.2 ± 0.2 mΩ · cm² compared to 6.93 ± 0.3 mΩ · cm² for thermally evaporated contacts. These deposition conditions were used to deposit front contacts onto high quality CIGS thin film photovoltaic cells. The heating required to print the Ag contacts caused the performance to degrade compared to similar devices with evaporated Ni/Al contacts that were not heated. Devices with inkjet printed contacts showed 11.4% conversion efficiency compared to 14.8% with evaporated contacts. Strategies to minimize heating, which is detrimental for efficiency, during inkjet printing are proposed. Copyright © 2011 John Wiley & Sons, Ltd.     

Characterization of a rapid thermal anneal TiNxOy/TiSi2 contact barrier

In this paper, the physical and electrical properties of a TiN_xO_y/TiSi₂ dual layer contact barrier are reported. The TiN_xO_y/TiSi₂ barrier was formed by rapidly annealing a Ti thin film on Si in an N₂ ambient. During this process, the Ti film surface reacts with N₂ to form a TiN_xO_y skin layer and the bulk of the Ti film reacts with Si to form an underlying TiSi₂ layer. The influences of rapid thermal anneal (RTA) conditions on the TiN_xO_y layer were investigated by varying the RTA temperature from 600 to 1100° C and cycle duration from 30 to 100 s. It is found that the resulting TiN_xO_y and TiSi₂ layer thicknesses are dependent on RTA temperature and the starting Ti thickness. For a starting Ti thickness of 500Å, 150Å thick TiN_xO_y and 800Å thick TiSi₂ are obtained after an RTA at 900° C for 30 s. The TiN_xO_y thickness is limited by a fast diffusion of Si into Ti to form TiSi₂. When a Ti film is deposited on SiO₂, Ti starts to react with SiO₂ from 600° C and a significant reduction of the SiO₂ thickness is observed after an RTA at 900° C. The resulting layer is composed of a surface TiN_xO_y layer followed by a complex layer of titanium oxide and titanium suicide. In addition, when Ti is depos-ited on TiSi₂, thicker TiN_xO_y and TiSi₂ layers are obtained after RTA. This is because the TiSi₂ layer retards the diffusion of Si from the underlying substrate into the Ti layer. NMOSFETs were fabricated using the TiN_xO_y/TiSi₂ as a contact barrier formed by RTA at 900° C for 30 s and a significant reduction of contact resistance was obtained. In addition, electromigration test at a high current density indicated that a significant improvement in mean time to failure (MTF) has been obtained with the barrier.     

The properties of photo chemical-vapor deposition SiO<Subscript>2</Subscript> and its application in GaN metal-insulator semiconductor ultraviolet photodetectors

High-quality SiO₂ insulating layers were successfully deposited onto GaN by a photo chemical-vapor deposition (photo-CVD) technique using a deuterium (D₂) lamp as the excitation source. The interface-trap density, D_it, was estimated to be 8.4×10¹¹ cm⁻²eV⁻¹ for the photo-CVD SiO₂ layers prepared at 300°C. It was found that the leakage current was only 6.6×10⁻⁷ A/cm² with an applied field of 4 MV/cm for the 300°C photo-CVD-grown Al/SiO₂/GaN metal-insulator semiconductor (MIS) capacitor. It was also found that the photo-CVD SiO₂ layer could be used to suppress the dark current of nitride-based photodetectors. A large photocurrent to dark-current contrast ratio higher than three orders of magnitude and a maximum 0.12 A/W responsivity were observed from the fabricated indium tin oxide (ITO)/photo-SiO₂/GaN MIS ultraviolet (UV) photodetectors. Furthermore, it was found that corresponding noise-equivalent power (NEP) and normalized detectivity, D*, of our ITO/photo-SiO₂/GaN MIS UV photodetectors was 2.19×10⁻⁹ W and 2.03 × 10⁸ cmHz_0.5W⁻¹, respectively, for a given bandwidth of 500 Hz.     

Fabrication of Cu(Ti) Alloy Interconnects with Self-Formation of Thin Barrier Metal Layers Using a High-Pressure Annealing Process

Copper interconnects with self-formed thin TiSi _x O _y barrier layers were successfully fabricated by sequentially depositing Cu(7 at.%Ti) alloys and pure Cu films on SiO₂-based substrates with 0.1-μm-wide trenches, and embedding the samples using a high-pressure annealing technique at 550°C and 195 MPa. Microstructural analyses revealed that the self-formed Ti-rich layers with thicknesses of about 5 nm were uniformly formed on the trench bottom and sidewall. In addition, these layers were thermally stable against Cu diffusion into the SiO₂-based interlayers. The present study suggests that the Cu-Ti alloy is one of the best candidates among possible interconnect and/or seed layer materials.     

High-resolution transmission electron microscopy of silicide formation and morphology development of Ni/Si and Ni/Si<Subscript>1−x</Subscript>Ge<Subscript>x</Subscript>

Nickel-silicide phase formation in the Ni/Si and Ni/Si_1−xGe_x (x=0.20) systems and its correlation with variations in sheet resistance have been studied using high-resolution transmission electron microscopy (HRTEM) and related techniques. Following a 500°C anneal, uniform and low-resistivity NiSi and NiSi_1−xGe_x (x<0.20) crystalline films were formed in the respective systems. Annealed at 900°C, NiSi₂, in the form of pyramidal or trapezoidal islands, is found to replace the NiSi in the Ni/Si system. After a 700°C anneal, threading dislocations were observed for the first time in the Ni/Si_1−xGe_x system to serve as heterogeneous nucleation sites for rapid lateral NiSi_1−xGe_x growth.     

The effect of Zn1‐xMgxO buffer layer deposition temperature on Cu(In,Ga)Se2 solar cells: A study of the buffer/absorber interface

The effect of atomic layer deposition temperature of Zn_1‐xMg_xO buffer layers for Cu(In,Ga)Se₂ (CIGS) based solar cell devices is evaluated. The Zn_1‐xMg_xO films are grown using diethyl zinc, bis‐cyclopentadienyl magnesium and water as precursors in a temperature range of 105 to 180°C. High efficiency devices are produced in the region from 105 up to 135°C. At a Zn_1‐xMg_xO deposition temperature of 120°C, a maximum cell efficiency of 15·5% is reached by using a Zn_1‐xMg_xO layer with an x‐value of 0·2 and a thickness of 140 nm. A significant drop in cell efficiency due to large losses in open circuit voltage and fill factor is observed for devices grown at temperatures above 150°C. No differences in chemical composition, structure and morphology of the samples are observed, except for the samples prepared at 105 and 120°C that show elemental selenium present at the buffer/absorber interface. The selenium at the interface does not lead to major degradation of the solar cell device efficiency. Instead, a decrease in Zn_1‐xMg_xO resistivity by more than one order of magnitude at growth temperatures above 150°C may explain the degradation in solar cell performance. From energy filtered transmission electron microscopy, the width of the CIGS/Zn_1‐xMg_xO chemical interface is found to be thinner than 10 nm without any areas of depletion for Cu, Se, Zn and O. Copyright © 2008 John Wiley & Sons, Ltd.     

Structural and Passivative Behaviors of Cu(In) Thin Film

This investigation prepares a low-resistivity and self-passivated Cu(In) thin film. The dissociation behaviors of dilute Cu-alloy thin films, containing 1.5–5at.%In, were prepared on glass substrates by a cosputter deposition, and were subsequently annealed in the temperature range of 200–600 °C for 10–30 min. Thus, self-passivated Cu thin films in the form In₂O₃/Cu/SiO₂ were obtained by annealing Cu(In) alloy films at an elevated temperature. Structural analysis indicated that only strong copper diffraction peaks were detected from the as-deposited film, and an In₂O₃ phase was formed on the surface of the film by annealing the film at an elevated temperature under oxygen ambient. The formation of In₂O₃/Cu/SiO₂ improved the resistivity, adhesion to SiO₂, and passivative capability of the studied film. A dramatic reduction in the resistivity of the film occurred at 500 °C, and was considered to be associated with preferential indium segregation during annealing, yielding a low resistivity below 2.92 μΩcm. The results of this study can be potentially exploited in the application of thin-film transistor–liquid crystal display gate electrodes and copper metallization in integrated circuits.     

Effect of erbium fluoride doping on the photoluminescence of SiO<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> films

The photoluminescence of SiO _x films deposited on c-Si wafers by the thermal evaporation of SiO in a vacuum and, for the first time, doped with ErF₃ by coevaporation is studied. It is shown that, like undoped SiO _x films, the unannealed SiO _x :ErF₃ films passivate the surface of the Si wafers and, thus, increase their edge photoluminescence intensity almost fivefold. A similar increase is observed after annealing of the doped films in air at 750°C. Doping with ErF₃ suppresses the photoluminescence of Si nanoclusters, if the films have been subjected to high-temperature annealing (at 750°C). In this case, the PL intensity of the band with a peak at ∼890 nm decreases as well. The ∼890 nm band is observed for the first time and, due to its features, is attributed to transitions in SiO _x matrix defects. The experimentally observed effect of ErF₃ doping on SiO _x film photoluminescence is interpreted. An intense photoluminescence signal from Er³⁺ ions in the nearinfrared spectral region (the ⁴ I _11/2 → ⁴ I _15/2 and ⁴ I _13/2 → ⁴ I _15/2 transitions) is observed in the SiO _x :ErF₃ films annealed in air at 750°C. This finding shows that 1.54 μm luminescent emitters, which are currently in popular demand, can be produced by a simple low-cost method.     

SiO<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> layer formation during plasma sputtering of Si and SiO<Subscript>2</Subscript> targets

Deposition of SiO _x layers of variable composition onto silicon wafers was performed by co-sputtering of spaced Si and SiO₂ targets in argon plasma. Coordinate dependences of the thickness and refractive index of separately deposited Si and SiO₂ layers and the SiO _x layer grown during co-sputtering of targets were determined using optical techniques. It was shown that the SiO _x layer composition is not equal to a simple sum of thicknesses of separately deposited Si and SiO₂ layers. The coordinate dependences of the Si and SiO₂ layer thicknesses were calculated. To fit the calculated and experimental data, it is necessary to assume that no less than 10% of silicon is converted to dioxide during co-sputtering. A comparison of the coordinate dependences of the IR absorbance in SiO₂ and SiO _x layers with experimental ellipsometric data confirmed the presence of excess oxygen in the SiO _x layer. Taking into account such partial oxidation of sputtered silicon, composition isolines in the substrate plane were calculated. After annealing of the SiO _x layer at 1200°C, photoluminescence was observed in a wafer area predicted by calculations, which was caused by the formation of quantum-size Si nanocrystallites. The photoluminescence intensity was maximum at x = 1.78 ± 0.3, which is close to the composition optimum for ion-beam synthesis of nanocrystals.     

Effects of Nb Content on the Ferroelectric and Dielectric Properties of Nb/Nd-Co-doped Bi<Subscript>4</Subscript>Ti<Subscript>3</Subscript>O<Subscript>12</Subscript> Thin Films

Nd/Nb-co-substituted Bi_3.15Nd_0.85Ti_3?x Nb _x O₁₂ (BNTN _x , x = 0.01, 0.03, 0.05 and 0.07) thin films were grown on Pt/Ti/SiO₂/Si (100) substrates by chemical solution deposition. The effects of Nb content on the micro-structural, dielectric, ferroelectric, leakage current and capacitive properties of the BNTN _x thin films were investigated. A low-concentration substitution with Nb ions in BNTN _x can greatly enhance its remanent polarization (2P _r) and reduce the coercive field (2E _c) compared with those of Bi₄Ti₃O₁₂ (BIT) thin film. The highest 2P _r (71.4 μC/cm²) was observed in the BNTN_0.03 thin film when the 2E _c was 202 kV/cm. Leakage currents of all the films were on the order of 10^?6 to 10^?5 A/cm², and the BNTN_0.03 thin film has a minimum leakage current (2.1 × 10^?6 A/cm²) under the high electric field (267 kV/cm). Besides, the C–V curve of the BNTN_0.03 thin film is the most symmetrical, and the maximum tunability (21.0%) was also observed in this film. The BNTN_0.03 thin film shows the largest dielectric constant and the lowest dielectric loss and its maximum Curie temperature is 410 ± 5°C.     

A dry-patterned Cu(Mg) alloy film as a gate electrode in a thin-film transistor liquid crystal display

The annealing of a Cu(4.5at.%Mg)/SiO₂/Si structure in ambient O₂ at 10 mtorr and 300–500°C allows for the out-diffusion of the Mg to the Cu surface, forming a thin MgO (15 nm) layer on the surface. The surface MgO layer was patterned and successfully served as a hard mask for the subsequent dry etching of the underlying Mg-depleted Cu films using an O₂ plasma and hexafluoroacetylacetone (H(hfac)) chemistry. The resultant MgO/Cu structure, with a taper slope of about 30°, shows the feasibility of dry etching of Cu(Mg) alloy films using a surface MgO mask scheme. A dry-etched Cu(4.5at.%Mg) gate a-Si:H thin-film transistor (TFT) has a field-effect mobility of 0.86 cm²/Vs, a subthreshold swing of 1.08 V/dec, and a threshold voltage of 5.7 V. A novel process for the dry etching of Cu(Mg) alloy films that eliminates the use of a hard mask, such as Ti, and results in a reduction in the process steps is reported for the first time in this work.     

Memory Effect of Metal-Insulator-Silicon Capacitor with HfO<Subscript>2</Subscript>-Al<Subscript>2</Subscript>O<Subscript>3</Subscript> Multilayer and Hafnium Nitride Gate

Metal-insulator-silicon capacitors have been fabricated using novel insulators of SiO₂/HfO₂-Al₂O₃-HfO₂ (HAH)/Al₂O₃ and metallic HfN gate, exhibiting a program-erasable characteristic. The memory capacitor presents a large memory window of 2.4 V under +12 V program/–14 V erase for 10 ms, no erase saturation, and sufficient electron- and hole-trapping efficiencies such as an electron density of ∼7 × 10¹² cm^–2 under 13 V program for 0.5 ms and a hole density of ∼4 × 10¹² cm^–2 under –12 V erase for 0.5 ms. The observed properties are attributed to the introduction of high permittivity atomic-layer-deposited HAH/Al₂O₃ as well as high work function HfN gate. The related mechanism is addressed accordingly.     

Enhanced Wettability of Oxidized Copper with Lead-Free Solder by Ar-H<Subscript>2</Subscript> Plasmas for Flip-Chip Bumping

Enhanced solder wettability (SW) of oxidized-Cu (OC) with 96.5Sn-3Ag-0.5Cu lead-free solder (LFS) by Ar-H₂ plasmas was investigated. The SW of OC was significantly improved from 0% wetting of Cu oxidized in air at 260°C for 1 h to 100% wetting of OC modified by Ar-H₂ plasmas for 10 min. The SW of Cu was found to be highly dependent on the surface characteristics of Cu. By decreasing the total surface energy (TSE), decreasing the polar surface energy (PSE), and increasing the dispersive surface energy (DSE) on the surfaces of OC modified by Ar-H₂ plasmas, the SW with LFS improves. X-ray photoelectron spectroscopy (XPS) indicates that Ar-H₂ plasma treatment is used to remove the copper oxides CuO and Cu₂O from the OC surfaces. The ratio of the total amount of Cu₂O to CuO was found to be a good indication of how the copper oxides CuO and Cu₂O affect the PSE, DSE, and SW of Cu.     

Improved Long-Term Thermal Stability At 350°C Of TiB2–Based Ohmic Contacts On AlGaN/GaN High Electron Mobility Transistors

AlGaN/GaN High Electron Mobility Transistors (HEMTs) were fabricated with Ti/Al/TiB₂/Ti/Au source/drain Ohmic contacts and a variety of gate metal schemes (Pt/Au, Ni/Au, Pt/TiB₂/Au or Ni/TiB₂/Au) and subjected to long-term annealing at 350°C. By comparison with companion devices with conventional Ti/Al/Pt/Au Ohmic contacts and Pt/Au gate contacts, the HEMTs with boride-based Ohmic metal and either Pt/Au, Ni/Au or Ni/TiB₂/Au gate metal showed superior stability of both source-drain current and transconductance after 25 days aging at 350°C.