Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

Optimization of nonplanar power MOS transistors

Analysis of fundamental MOSFET parameters predicts device limits in high-voltage high-speed operation that exceed the performance of bipolar devices. The optimization of voltage, speed, and "on" resistance parameters for power MOSFET's suggests a vertical three-terminal device design with short, wide channels; a wide, lightly doped drain region; and field terminator rings at the device perimeter. Utilizing this design philosophy, VMOS transistors have been produced with source-drain breakdown voltage greater than 450 V, and 5.5-Ω "on" resistance for 2.0-mm²active area. With a high channel width packing density design and 2.5-mm²active area, a 30-V transistor has also been produced having only 0.060-Ω "on" resistance. The breakdown voltage and "on" resistance of these devices exceed the performance of other power MOSFET's currently available. Also, the switching speed of these devices (better than 15 ns) far exceeds the performance of high-voltage bipolar transistors. Measurements of drain leakage current at 200-V drain potential show a resistance ratioR_{off}/R_{on}of approximately 10¹⁰for a 20-V variation in gate-to-source voltage.     

The insulated gate transistor: A new three-terminal MOS-controlled bipolar power device

A new three-terminal power device, called the insulated gate transistor (IGT), with voltage-controlled output characteristics is described. In this device, the best features of the existing families of bipolar devices and power MOSFET's are combined to achieve optimal device characteristics for low-frequency power-control applications. Devices with 600-V blocking capability fabricated using a vertical DMOS process exhibit 20 times the conduction current density of an equivalent power MOSFET and five times that of an equivalent bipolar transistor operating at a current gain of 10. Typical gate turn-off times have been measured to range from 10 to 50 µs.     

Bipolar structures for BIMOS technologies

Recent advances in LSI and VLSI have offered many possibilities in mixing MOSFET and bipolar integrated structures on the same chip. The authors study the integration of bi-polar structures in BIMOS environments. More specifically bipolar structures are studied under the constraints and guidelines of a given MOS technology, e.g., the nonexistence of an n/SUP +/ underlayer, and the high epitaxial (substrate) resistivity. A bipolar structure, based on merging a multicollector p-n-p transistor with a multiemitter n-p-n transistor is proposed. The structure takes advantage of the availability of clock signals on a MOS chip, and uses the epitaxial (substrate) resistance as a load. It can be used to realize logic and memory functions. Computer simulation as well as experimental results show that the structure can perform efficiently in both BIMOS and bipolar technologies.     

Bipolar transistor epilayer design using the MAIDS mixed-levelsimulator

In this paper, we address the epilayer design of the bipolar transistor using the one-dimensional (1-D) mixed-level simulator MAIDS (microwave active integral device simulator). MAIDS facilitates simulation of the electrical behavior of bipolar (hetero) junction transistors with various doping profiles and under different signal conditions in a realistic circuit environment. MAIDS as implemented within Hewlett Packard's microwave design system is a useful and promising tool in the development of bipolar transistors for large-signal conditions. Using MAIDS, we have identified the dominant bipolar transistor distortion sources with respect to the biasing conditions. Simulation results are compared with small- and large-signal measurements for the BFQ135 transistor, which has been developed for cable television (CATV) applications. By analyzing the measured and simulated data, we have developed an optimum epilayer design map for third-order intermodulation distortion that has proven to be particularly useful in the epilayer dimensioning of transistors for CATV applications     

Transformerless capacitive coupling of gate signals for seriesoperation of power MOS devices

A reliable configuration for triggering a series string of power metal oxide semiconductor (MOS) devices without the use of transformer coupling is presented. A capacitor is inserted between the gate and ground of each metal oxide semiconductor field effect transistor (MOSFET), except for the bottom MOSFET in the stack. Using a single input voltage signal to trigger the bottom MOSFET, a voltage division across the network of device capacitance and inserted capacitances triggers the entire series stack reliably. Design formulas are presented and simple circuit protection is discussed. Simulation shows reliable operation and experimental verification is presented, Application of the method is applied to series insulated gate bipolar transistors (IGBTs)     

IGBT SPICE model

During the last few years, great progress in the development of new power semiconductor devices has been made. The new generation of power semiconductors is capable of conducting more current and blocking higher voltage. The IGBT (insulated gate bipolar transistor) is an outgrowth of power MOSFET technology. More like a MOSFET than a bipolar transistor in structure, the IGBT has some of the electrical characteristics of both. Like a MOSFET, the gate of the IGBT is isolated, and drive power is very low. The on-state conduction voltage of an IGBT is similar to that of a bipolar transistor. However, SPICE users are constantly faced with the inability to analyze circuits that contain devices that are not in the SPICE library of the semiconductor models. With the authors' own computer program, a complete macromodel of the IGBT for the SPICE simulator has been computed. In this paper, a complete IGBT SPICE macromodel is described and verified with experimental results     

Optimizing the match in weakly inverted MOSFET's by gated lateralbipolar action

The on-chip n-type MOSFET current mirror circuit with different drawn gate widths and lengths has been fabricated, and has been characterized across the wafer with back gate slightly forward biased. The weakly inverted MOSFET device with a small back-gate forward bias represents equivalently the high-gain gated lateral bipolar transistor in low-level injection. Experimental results have exhibited a substantial improvement in the match of the drain current in weak inversion due to action of the gated lateral bipolar transistor, especially for the small size devices. The extensively measured mismatch of the weak inversion drain current has been successfully reproduced by an analytic statistical model with back-gate forward bias and device size both as input parameters. The experimentally extracted variations in process parameters such as the flat-band voltage and the body effect coefficient each have been found to follow the inverse square root of the device area. The mismatch model thus can serve as a quantitative design tool, and has been used to optimize the trade-off between the device area and the match with the forward back-gate bias as a parameter     

Reverse bipolar transistor conduction in high-current PWM inverters

Most PWM (pulse width-modulated) inverters using bipolar transistors experience the problem of reverse transistor conduction. This effect is analyzed for various types of base drives. It is shown to be the most serious for low-impedance direct drives. A model is developed for this case and verified experimentally. Problems associated with turn-on and turn-off in the reverse conduction mode are investigated. Various base drives, including both direct drives and Darlington configurations, are analyzed. Reverse transistor conduction is found to have the most serious implications for transistors driven directly by a low impedance source. Although discrete devices are discussed, the results also apply to integrated Darlington modules     

A bipolar lock-layer transistor

A bipolar transistor and a junction field effect transistor are integrated into a “merged” cascode configuration. Viewed as a modified bipolar transistor, this device has a new and favorable combination of common-emitter breakdown voltage and current gain, and is largely free of the Early effect.     

MOS-Based Spin Devices for Reconfigurable Logic

Semiconductor-based spin transistors are expected to give a new spin degree of freedom in future electronics. While many different spin transistors have been proposed and studied, the spin MOSFET is one of the most promising devices, because it can have spin-dependent output characteristics, transistor functions, and good compatibility with existing silicon technology. The device concept, structures of various types of spin MOSFETs, operation principles, calculated output characteristics, and applications was reviewed. It is shown that the output characteristics of the spin MOSFETs depend on the relative magnetization configuration of the two ferromagnetic layers in the device, that is, high current-drive capability in parallel magnetization and low current-drive capability in antiparallel magnetization. Furthermore, nonvolatile memory and reconfigurable logic gates was presented using spin MOSFETs, where the logic functions can be changed by switching their magnetization configurations. Circuit design and numerical simulations of reconfigurable gates for NAND/NOR, AND/OR, and all symmetric Boolean functions was shown     

Criteria for setting the width of CCD front end transistor to reachminimum pixel noise

The paper gives the criteria to calculate the width of the front end transistor integrated next to the charge sensing electrode of CCDs or, in general, of semiconductor detectors, in order to reach the minimum noise in the readout of the signal charge. It accounts for white, series and parallel, and 1/f noise contributions. In addition, it points out two different design criteria depending whether a JFET or a MOSFET is used. The attention given to the JFET is due to a lower 1/f noise component, which makes these transistors more appealing as input devices in very high resolution detectors. The paper shows that there is a characteristic width of the FET gate that practically does not depend on the noise sources but depends only on the capacitance seen by the charge sensing electrode of the detector, making possible the optimum design of the transistor prior to knowledge of the real values of the spectral density of the noise sources, which are usually precisely known only at the end of the fabrication process. The paper shows that the pixel noise raises sharply as the transistor gate width departs from its optimum value     

Evaluation of graded-channel SOI MOSFET operation at high temperatures

This paper presents a comparative analysis between graded-channel (GC) and conventional fully depleted SOI MOSFETs devices operating at high temperatures (up to 300 °C). The electrical characteristics such as threshold voltage and subthreshold slope were obtained experimentally and by two-dimensional numerical simulations. The results indicated that GC transistors present nearly the same behavior as the conventional SOI MOSFET devices with similar channel length. Experimental analysis of the g_m/I_DS ratio and Early voltage demonstrated that in GC devices the low-frequency open-loop gain is significantly improved in comparison to conventional SOI devices at room and at high-temperature due to the Early voltage increase. The multiplication factor and parasitic bipolar transistor gain obtained by two-dimensional numerical simulations allowed the analysis of the breakdown voltage, which was demonstrated to be improved in the GC as compared to conventional SOI transistors in thin silicon layer devices in the whole temperature range under analysis.     

A resonant converter suitable for 650 V DC bus operation

A high-frequency resonant power converter configuration suitable for operation on a 650 V (nominal value) DC bus is described. Selection of the high-frequency switch and an appropriate resonant configuration are discussed. It is shown that a series-parallel resonant converter using insulated gate bipolar transistor (IGBT) gated bipolar/MOSFET cascode switches and operating above resonance is suitable for this application. A simplified analysis, a simple design procedure, and detailed experimental results are presented     

CASFET: A MOSFET-JFET cascode device with ultralow gate capacitance

A field-effect transistor is described that combines a short-gate MOSFET with a long-channel JFET in a cascode configuration. The composite device, a CASFET, can have a very low input capacitance due to the short gate of the MOSFET combined with the reduced Miller capacitance of the cascode. The long channel of the JFET insures that the CASFET has high output resistance. This paper discusses CASFET fabrication, performance, and modeling.     

An introduction to GaAs/GaAlAs HBTs for power applications

This paper presents a brief introduction to GaAs/GaAlAs heterojunction bipolar transistors (HBTs) for microwave and millimetre-wave power applications. The theoretical advantages of the heterojunction are outlined and the benefits of its incorporation in DC, RF and power devices are discussed. The problems inherent in the realization of HBTs in terms of device design, epitaxial material growth and device fabrication are discussed and the performance characteristics for practical devices presented. The paper concludes with a look at state-of-the-art GaAs/GaAlAs HBT performance and its standing with respect to the competing technologies of the metal semiconductor field effect transistor (MESFET) and the high electron mobility transistor (HEMT).     

The Complete Semiconductor Transistor and Its Incomplete Forms

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor,BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.     

Optimization and scaling of CMOS-bipolar drivers for VLSI interconnects

In this paper, rules are presented for the optimized design of CMOS-bipolar drivers for large capacitive loads typical of VLSI interconnects. Simulations and closed-form solutions show that the n-p-n bipolar transistors have to be operated in the high-level injection mode, and that their sizes have to be tailored to the two-thirds power of the load, and it scales with the two-thirds power of the base width of the n-p-n transistor and with the one-third power of the channel length of the MOS transistor. For comparison, the CMOS cascade with a tailored second stage is shown to have competitive potential at the expense of an area being approximately 2.5 times larger than that of a CMOS-bipolar stage.     

Transistor equivalent circuits

This paper surveys the history of the electric-circuit representation of the transistor over the past fifty years. During the first two decades after the transistor was announced in 1948, primary emphasis was on small-signal equivalent circuits, which could be used for linear-circuit analysis and design. In addition, parameters of many of these equivalent circuits for the bipolar junction transistor, which are described, were related to the physical construction of the device. Approximately two-thirds of the paper is devoted to this period, when the writer personally contributed to this effort. By the beginning of the third decade, transistor circuits had became more complex, and circuit analysis was carried out with the help of digital computers. Interest then shifted away from small-signal equivalent circuits to “models” for computer-aided circuit design (CACD). This transition, including the models used in the widely used CACD program SPICE, is described. MOS transistors are treated only briefly; by the time MOS transistors became commercially viable devices, emphasis then also had shifted to “models” for CACD. In conclusion, the writer notes that there is still hope for us aficionados of small-signal equivalent circuits; new types of transistors are still being characterized in this manner     

PMOS input merged bipolar/sidewall MOS transistors (PBiMOStransistors)

A concept of merging vertical n-p-n bipolar and sidewall PMOS transistors into merged PBiMOS transistors is described. This concept allows device structures which perform more complex functions to be integrated into a given area. The feasibility of this concept is demonstrated by fabricating and DC characterizing PBiMOS transistor structures which occupy ~1.1 times the area of a single n-p-n bipolar transistor. The PMOS sidewall transistor characterization results suggest that a reasonable control of the key device parameters may be achieved. These results also suggest that, for the 23-nm gate oxide thickness, the doping requirements for the n^- collector of the n-p-n bipolar and the channel of the sidewall PMOS transistors are similar