基于不同测量手段的纳米晶器件的存储特性

对纳米晶器件,尤其是MOS电容进行了横截面TEM分析和不同条件下的电学特性(C-V特性)测量,包括+/-BT分析. 揭示了系统的纳米晶存储物理机制,例如电荷俘获、界面态填充和温度特性. 研究结果表明,高温、大电压摆幅和偏置情况下,器件编程窗口的恶化和阈值电压的漂移与多数载流子的种类有关.     

基于不同测量手段的纳米晶器件的存储特性

对纳米晶器件,尤其是MOS电容进行了横截面TEM分析和不同条件下的电学特性(C-V特性)测量,包括 /-BT分析. 揭示了系统的纳米晶存储物理机制,例如电荷俘获、界面态填充和温度特性. 研究结果表明,高温、大电压摆幅和偏置情况下,器件编程窗口的恶化和阈值电压的漂移与多数载流子的种类有关.     

Quasi-static behavior of MOS devices in the freeze-out regime

The quasi-static CV curves (low-frequency C-V curves) measured in the freeze-out regime of MOS transistors result in peaks near the accumulation or inversion regions depending on the direction of the voltage sweep. In this paper, we report a study of these peaks in n- and p-channel CMOS transistors within and outside compensating wells. The peaks in the quasi-static CV curves are attributed to the capture of minority carriers near inversion by the interface states and the capture of majority carriers by the interface states near accumulation     

有限介质绝缘电阻对C—V测量的影响

本文描述了在高频和准静态C-V测量中,二氧化硅介质层有限电阻对测量准确性的影响。特别是在准静态测量中,由于频率相当低,MOS电容值只有100pF左右,所产生的位移电流为10(-9)～10(-14)A范围,介质层有限电阻产生的漏电流对测量准确性影响很大。因此,在存在漏电流的情况下,必须从测得的数值中扣除漏电流,才能进行界面态密度的计算。     

Low-temperature hysteresis effects in metal-oxide-silicon capacitors caused by surface-state trapping

At low temperatures, charge exchange in all surface states except those close to the band edges can occur only by capture of free carriers because emission rates become very slow. If means are provided to supply minority carriers (either from an extended inversion layer or in a gate-controlled diode), pronounced charge-trapping effects can be observed. A ledge in the C-V characteristic is identified as being due to the charging of almost all surface states within the forbidden gap at a surface potential dependent on surface-state density, capture cross section and voltage sweep rate. Capture cross sections at low temperatures can be estimated from the onset of the ledge. When the C-V curves are traced from accumulation to inversion the capacitance drops below the equilibrium minimum value into depletion and increases rapidly when inversion is reached. This "hook" is caused by a barrier against minority carrier flow at the boundary of the MOS capacitor. The barrier disappears when sufficient voltage is applied to charge the surface states in the boundary region.     

Capacitance-voltage characterization of fully silicided gated MOS capacitor

This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leak-age current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic, A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.     

Capacitance-Voltage measurement method for ultrathin gate dielectrics using LC resonance circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.     

C-t analysis of MOS capacitors under constant current stress

The effect of high oxide field stress is studied using capacitance-time (C-t) measurements of MOS capacitors. The stress results in parallel shifts of the C-t curve along the time axis. The flatband voltage shift ΔV_FB obtained from the initial deep depletion capacitance C(t=0⁺) follows the same trend as that from the high-frequency C-V characteristics. However, the discrepancy between the two flatband voltages becomes larger as the stress increases due to the effect of interface charges on C-t characteristics. The flatband voltage difference is converted to interface trap density, showing a steady increase of interface trap density with stress, similar to that from low-frequency C-V measurements     

非均匀掺杂衬底MOS结构少子产生寿命的测量

本文分析了非均匀掺杂衬底MOS电容对线性扫描电压的瞬态响应,提出了三角波C-V技术测量非均匀掺杂MOs电容少子产生寿命的方法.该方法简单、且不需知道衬底的掺杂分布.     

SiC隐埋沟道MOS结构夹断模式下的C-V特性畸变

用数值和解析的方法研究了SiC隐埋沟道MOS结构夹断模式下C-V特性的畸变.隐埋沟道MOSFET中存在一个pn结,在沟道夹断以后,半导体表面耗尽区和pn结耗尽区连在一起,这时总的表面电容是半导体表面耗尽区电容和pn结电容的串联,使埋沟MOS结构的C-V特性发生畸变.文中通过求解泊松方程,用解析的方法分析了这种畸变发生的物理机理,并对栅电容进行了计算,计算结果与实验结果符合得很好.     

Determination of generation lifetime from non-equilibrium linear-sweep current and capacitance measurements on an MOS capacitor

A simple, fast and accurate method to obtain the generation lifetime is presented. The method is based on measuring both the current and the capacitance of an MOS capacitor in response to a depleting linear voltage ramp, started in inversion. Its advantages compared to already existing methods are the small time needed for a complete lifetime measurement, the low gate voltages during the sweep and the ease of combination with quasi-equilibrium C-V measurements.     

A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

Interface trap densities at gate oxide/silicon substrate (SiO₂/Si) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.     

Dopant profile and gate geometric effects on polysilicon gatedepletion in scaled MOS

Polysilicon depletion effects show a strong gate length dependence according to experimental p-channel MOS capacitance-voltage (C-V) data. The effect can be influenced not only by gate geometries, but also by dopant profiles in poly-gates. These effects have been modeled and verified using device simulation. Nonuniform dopant distributions in the vertical and lateral direction in the poly-gate cause additional potential drops. The potential drop in the poly-gate becomes critical as the gate geometry is scaled down due to edge and corner depletions resulting from fringing electric fields     

Determination of recombination lifetime in MOS structures by a sine voltage-sweep technique

A sine-voltage technique for measurements of recombination lifetime in metal oxide semiconductor (MOS) structures is proposed. When a fast sine-voltage sweep ramp is applied to the gate of an MOS capacitor a non-equilibrium depletion layer is formed and electron–hole generation starts in the space–charge–region and in the bulk. If the measurements are performed at elevated temperature so that quasi-neutral region generation rather than space charge region generation dominates, then the diffusion length, consequently the recombination lifetime, can be determined.     

Measurement of MOSFET substrate dopant profile via inversionlayer-to-substrate capacitance

In this paper, a new method for extracting substrate dopant concentration profile of short-channel MOSFET's is presented. It is based on the measurement of the small-signal capacitance between the inversion layer and the substrate. The method achieves effective deep depletion through dc reverse bias on the inversion-to substrate junction and thus avoids the problems with transients associated with pulsed C-V of MOS capacitors. By using transistors of different drawn lengths the effect of lateral extension of drain and source junction depletion regions is also accounted for     

Estimating oxide thickness of tunnel oxides down to 1.4 nm usingconventional capacitance-voltage measurements on MOS capacitors

High-frequency capacitance-voltage (C-V) measurements have been made on ultrathin oxide metal-oxide-semiconductor (MOS) capacitors. The sensitivity of extracted oxide thickness to series resistance and gate leakage is demonstrated. Guidelines are outlined for reliable and accurate estimation of oxide thickness from C-V measurements for oxides down to 1.4 nm     

Application of junction capacitance measurements to the characterization of solar cells

The quasi-static capacitance-voltage ( C-V) technique measures the dependence of junction capacitance on the bias voltage by applying a slow, reverse-bias voltage ramp to the solar cell in the dark, using simple circuitry. The resulting C-V curves contain information on the junction area and base dopant concentration, as well as their built-in potential. However, in the case of solar cells made on low to medium resistivity substrates and having thick emitters, the emitter dopant profile has to be taken into account. A simple method can then be used to model the complete C-V curves, which, if the base doping is known, permits one to estimate the emitter doping profile. To illustrate the method experimentally, several silicon solar cells with different base resistivities have been measured. They comprise a wide range of areas, surface faceting conditions and emitter doping profiles. The analysis of the quasi-static capacitance characteristics of the flat surface cells resulted in good agreement with independent data for the wafer resistivity and the emitter doping profile. The capacitance in the case of textured surfaces is a function of the effective junction area, which is otherwise difficult to measure, and is essential to understand the emitter and space charge region recombination currents. The results indicate that the effective area of the junction is not as large as the area of the textured surface.     

The exact low-frequency capacitance-voltage characteristics of metal-oxide-semiconductor (MOS) and semiconductor-insulator-semiconductor (SIS) structures

Accurate low-frequency MOS (metal-oxide-semiconductor) and SIS (semiconductor-insulator-semiconductor) C-V curves are found by solving Poisson's equation in the bulk semiconductor using regions of analytic solution joined by numerical solutions of specified accuracy. The technique uses the full Fermi function for the electron, hole, and impurity bands; thus valid results can now be obtained for partially ionized impurity bands, and situations in which the valence or conduction bands are bent through the Fermi level. The calculation can be carried out for any temperature and allows for band structure in the valence and conduction bands. Surface states are incorporated at the interface and the usual low-frequency capacitance curves are obtained for the MOS device. As expected, the C-V curves in the SIS case are more complex. The n-i-n (n-type semiconductor, insulator, n-type semiconductor) device shows two depletion minima separated by a center maxima whose size is sensitive to surface-state charge. In the p-i-n device, the depletion minima can be seen separately only if the impurity concentrations of the semiconductors differ by a factor of five or more. In that case, a deep narrow minimum due to the lightly doped semiconductor can be seen superimposed on one end of a broad shallow minimum due to the heavily doped semiconductor. This work predicts an interesting high-frequency response for the n-i-n structure, namely a bell-shaped C-V curve. This type of C-V response has not been observed to date in two-terminal passive devices, and may lead to SIS applications as a new type of parametric capacitor.     

Characterization of MOS structures based on poly (3,3'-dialkyl-quaterthiophene)

Metal-polymer-oxide-silicon (MPOS) structures with poly(3,3'-dialkyl-quaterthiophene) as an active semiconductor layer have been characterized by means of capacitance-voltage (C-V) methods at different ramping rates (dV/dt) for the voltage sweep in the quasi-static capacitance-voltage method (QCV), and at different frequencies (f) for the dynamic or high-frequency method (DCV or HCV). The observed dependency of the capacitance on ramping rate and frequency are explained with a frequency dependent carrier enhancement and a long relaxation time constant in the polymer. The surface modification of gate oxide is found to improve the carrier enhancement in the active polymer layer of MPOS.     

Activation energy determination from low-temperature CV dispersion[semiconductor devices]

The response of semiconductor devices at low temperatures to changes in the voltage across the depletion region is limited by the dielectric relaxation time of the majority carriers in the bulk region. This results in a dispersion of the C-V curves at low temperatures. In this paper, we report a study of the dispersion seen in the accumulation and depletion regions of the C-V curve in n- and p-channel MOS transistors as well as in reverse biased one-sided abrupt junctions. From the admittance measured as a function of temperature and frequency, the dopant energy level is determined. The values of the activation energy measured using the diodes agree well with the corresponding values obtained using MOS devices