A study of analog decision feedback equalization for ADC-Based serial link receivers

High-speed serial link receivers based on analog-to-digital converters (ADCs) provide better programmability with different channel characteristics and the possibility of employing powerful signal equalization techniques in the digital domain. However, complexity and power consumption are still major issues in adopting such receivers in high-speed applications when compared to traditional binary or mixed-signal approaches. Embedded decision feedback equalization (DFE) before ADC quantization can relax the design requirements of both the ADC and post-ADC digital processing. This paper studies the impact of embedded analog DFE on voltage margin improvement of an ADC-based receiver through worst-case analysis. An analytical expression for the link bit-error-rate (BER) with analog DFE is derived and validated through simulations. An empirical study is conducted that evaluates the achievable BER of embedded analog DFE as a function of the channel inter-symbol interference (ISI) and ADC resolution. A channel-dependent parameter is introduced and employed to quantify the BER improvement achieved by embedding analog DFE in a receiver. A prototype receiver with embedded DFE is designed and laid out in a 130 nm CMOS process and achieves 4.64-bits peak ENOB and 4.08 pJ/conv.-step FOM at a 1.6-GS/s sampling rate. The BER performance of the receiver over high-loss FR4 channels at 1.6 Gb/s is evaluated and used to validate the simulation results.     

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally     

Decision Feedback Equalization for Multipath Induced Interference in Digital Microwave LOS Links

The performance of a 49-QPRS, 90 Mbit/s digital radio receiver equipped with a decision feedback equalizer (DFE) to counter multipath fading is investigated via computer simulation. The simulation includes the transmitted data, multipath fade model, receiver model, and DFE. The results indicate that a DFE equipped with five forward and five feedback taps can adequately compensate a 40 dB minimum-phase fade anywhere in the receiver passband. The study is extended to other receiver configurations including the use of space diversity and/or slope equalizers and the use of a transversal equalizer (TE) with the same delay-span in place of the DFE. The results indicate that the DFE equipped receiver outperforms the TE receiver and that still better performance may be achieved using a combination of space diversity and DFE.     

A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization

A 5-bit 4.8 GS/s 4-way time-interleaved ADC is designed for a receiver front-end in a 0.13 $muhbox{m}$ CMOS technology. Each time-interleaved ADC uses look-ahead pipelined stages to enable higher sample rates and more linear residue characteristics than a conventional pipeline ADC. At 1.2 GHz per path, the residue amplifiers settle to 75% of their final value, however, the linear residue characteristics allows using digital reference calibration to enable 30.4 dB of SNDR with a 1.2 MHz input signal. A capacitor pre-charging technique reduces the memory effect errors of the incompletely settled residue to 2% of the stage output swing. The peak INL and DNL are measured as 0.65LSB and 0.55LSB, respectively. The measured ERBW is ${sim},$ 6.1 GHz. The ADC, including the reference buffers, consumes 300 mW from a 1.2-V supply while operating at 4.8 GHz conversion rate. A stage-by-stage feedback compensates the possible bandwidth limitation of the system using a per-stage speculative DFE. The DFE tap is adjustable between 0 and 0.4 using 8 control bits.      

Joint preprocessing and feedback strategies for perfectly reconstructing equalizers

In this paper we consider the transmission of discrete-valued data via a communication channel that is subject to (additive) noise with a known upper bound on its magnitude but otherwise completely unrestricted and unknown behavior. We consider a discrete-time setup and extend previous equalization strategies for perfect reconstruction by allowing linear preprocessing of the data and/or linear feedback from the receiver to the transmitter. We are interested in the characterization of general conditions that allow perfect reconstruction of the discrete data with any given (possibly nonzero) delay (and under all possible realizations of channel noise and a limit on the power of transmission) when linear preprocessing of the data and/or linear feedback from the receiver is employed. In particular, we obtain necessary and sufficient conditions for perfect reconstruction under either linear power-limited preprocessing or linear power- limited preprocessing along with linear feedback. We prove that in order to improve the conditions for perfect reconstruction, it is necessary that the feedback and preprocessing systems are unstable. We also consider the case when a Decision Feedback Equalizer (DFE) structure is imposed at the receiver and provide necessary conditions for improvements in the perfect reconstruction in terms of l¹ norms of appropriate maps. In addition, a procedure that results in parametric l¹ optimization is developed to design a DFE to improve the maximum tolerable noise bound.     

Sequence estimation techniques for digital subscriber looptransmission with crosstalk interference

The use of reduced-state sequence estimation techniques in a digital subscriber loop receiver is discussed. These techniques offer a potential performance improvement over conventional equalization techniques such as decision feedback equalization (DFE). Stationary and cyclostationary NEXT noise models are described. The theoretical performance obtainable from a Viterbi algorithm receiver with stationary white Gaussian noise, stationary NEXT, and cyclostationary NEXT noise models is estimated, and the reduced-state decision feedback sequence estimation and M algorithms are reviewed. It is shown that the improvement can be especially significant in the presence of cyclostationary crosstalk because of the freedom that sequence estimation receivers afford in the choice of receiver sampling phase. This advantage is evaluated for Viterbi algorithm receivers. By simulation of two practical reduced-state sequence estimation receivers, it is demonstrated that, in the presence of cyclostationary crosstalk, a substantial increase in maximum loop range (or equivalently, maximum bit rate) may be achievable compared to conventional DFE equalization     

Interference cancellation enhancement through generalized widely linear equalization in QAM systems

In this paper, we introduce a generalized widely linear (WL) equalizer for quadrature amplitude modulation (QAM) systems with single/multiple antennas. In our proposed implementation, the WL receiver first separates the in-phase (I) and quadrature (Q) parts of the complex-valued baseband received signal and jointly filters the two branches for signal detection. Infinite length WL minimum mean-square error (WL-MMSE) linear, and WL decision-feedback-equalizer (WL-DFE) settings are derived and performance is analyzed in co-channel interference limited channels. It is shown that, in frequency selective Rayleigh fading channels, the interference cancellation (IC) gain depends mainly on the rank (r) of the interference correlation matrix (ICM) which is defined as the covariance of the vector-valued signal which consists of the real and imaginary parts of the noise-plus-interference signal collected at multiple antenna branches. Assuming that the DFE feedback path is error free, we show that a WL QAM receiver with N antennas exhibits full IC capability (that is complete interference removal) when the ICM is rank deficient i.e., when: r ≪ 2N. This condition implies that a WL-DFE receiver can reject any combination of M1 pulse-amplitude-modulation (PAM) and M2 QAM interferers satisfying the constraint: M1 + 2M2 ≪ 2N. Simulation results show that, in the presence of PAM-type interference, the gain of WL-DFE is reduced by decision feedback errors while the IC benefit of WL-MMSE is limited by the noise enhancement problem. Nevertheless, the proposed receivers are shown to be useful in cellular systems that employ a combination of PAM and QAM schemes.     

Cyclostationary crosstalk suppression by decision feedbackequalization on digital subscriber loops

Interference from digital signals in multipair cables has been shown to be cyclostationary under some conditions. This work evaluates the performance of a decision feedback equalizer (DFE) in the presence of cyclostationary interference (CI), intersymbol interference (ISI), and additive white noise (AWN). A comparison between a DFE with CI and one with stationary interference (SI) shows the ability of the DFE to substantially suppress CI. Fractionally spaced and symbol-rate DFE equalizers are also compared and the former is found to yield better performance, especially in the presence of CI. The use of a symbol-rate DFE using an adaptive timing technique that finds the receiver's best sampling phase is proposed for when the fractionally spaced DFE cannot be used because of its complexity. The results also demonstrate the potential benefits of synchronizing central office transmitter clocks, if a fractionally spaced DFE is used at the receiver     

Performance of a dual-rate DS-CDMA-DFE in an overlaid cellularsystem

The performance of a direct-sequence code-division multiple-access (DS-CDMA) system in an overlaid cell environment using a decision feedback equalizer (DFE) receiver is presented. It is shown that a DFE receiver can separate the desired signal from several interfering signals without any loss in the overall capacity. The results indicate that DS-CDMA with a DFE receiver can be used to integrate dual-rate services without adversely affecting the system capacity. The overall system capacity is shown to be approximately equal to half the spreading gain and is unaffected when interferers at different data rates are present. The proposed scheme needs only average power control and is not found to be sensitive to power control errors of ±2 dB     

An analog DFE for disk drives using a mixed-signal integrator

An analog adaptive decision-feedback equalizer (DFE) is described. The DFE cancels intersymbol interference using four feedback taps, and a fifth tap cancels dc offset. The coefficient for each tap is adapted using a small mixed-signal integrator. The DFE dissipates 220 mW at a data rate of 150 Mb/s. The active area is 1.8 mm² in a 1-μm CMOS process     

Adaptive DFE for GMSK in indoor radio channels

We simulate the performance of an equalized Gaussian minimum shift keying (GMSK) signal in an indoor radio environment with fading, noise, imperfect carrier recovery, cochannel interference (CCI), and intersymbol interference (ISI). We show that data rates of 20 Mb/s at bit error rates (BER) ⩽10^-4 are possible with root mean square (RMS) delay spreads up to 25 ns using a simple limiter-discriminator-integrator (LDI) receiver and a (6, 4) decision feedback equalizer (DFE). In environments with larger RMS delay spreads, coherent detection is required for the same performance. We show that using a decision-directed second-order digital carrier synchronizer with time varying loop filters, frequency offsets up to 200 kHz can be corrected with negligible performance degradation. This paper utilizes a DFE structure which compensates for both modulator and channel ISI, and yet requires no power-intensive multiplication operations in the feedback section. A DFE (8, 8) with two-level switched (selection) diversity is shown to allow 20 Mb/s data transfer at a BER⩽10^-4 for RMS delay spreads under 150 ns, with CCI. A light BCH (26, 31) code allows error-free reception of over 90% of packets with RMS delay spreads under 150 ns, and up to 70% of packets with RMS delays of 150 ns     

4 Gbit/s receiver with adaptive blind DFE

A serial backplane receiver with adaptive blind decision feedback equalisation (DFE) is proposed, which can operate at up to 4 Gbit/s over 1.2 m distance, which includes discontinuities due to the packaging and backplane connectors. A reduced complexity DFE implementation is achieved by biasing high-speed comparators. DFE coefficient calculation is not performed on every consecutive received sample, which significantly reduces the design complexity and power consumption.     

Decision feedback equalization

As real world communication channels are stressed with higher data rates, intersymbol interference (ISI) becomes a dominant limiting factor. One way to combat this effect that has recently received considerable attention is the use of a decision feedback equalizer (DFE) in the receiver. The action of the DFE is to feed back a weighted sum of past decision to cancel the ISI they cause in the present signaling interval. This paper summarizes the work in this area beginning with the linear equalizer. Three performance criteria have been used to derive optimum systems; 1) minimize the noise variance under a "zero forcing" (ZF) constraint i.e., insist that all intersymbol interference is cancelled, 2) minimize the mean-square error (MMSE) between the true sample and the observed signal just prior to the decision threshold, and 3) minimize the probability of error (Min Pe). The transmitter can be fixed and the receiver optimized or one can obtain the joint optimum transmitter and receiver. The number of past decisions used in the feedback equalization can be finite or infinite. The infinite case is easier to handle analytically. In addition to reviewing the work done in the area, we show that the linear equalizer is in fact a portion of the DFE receiver and that the processing done by the DFE is exactly equivalent to the general problem of linear prediction. Other similarities in the various system structures are also shown. The effect of error propagation due to incorrect decisions is discussed, and the coaxial cable channel is used as an example to demonstrate the improvement available using DFE.     

A 35 Mb/s mixed-signal decision-feedback equalizer for disk drivesin 2-μm CMOS

A 35 Mb/s mixed-signal adaptive decision-feedback equalizer (DFE) has been implemented in a 2-μm CMOS technology. The DFE has four feedback taps for cancelling intersymbol interference (ISI) and one tap for cancelling dc offset. The ISI is cancelled using fully differential analog circuits. Coefficient adaptation is digital, and two adaptation rates are available. The DFE occupies 24 mm² and dissipates 165 mW     

Innovative pulse shaping for high-performance wireless TDMA

This letter introduces a novel pulse shaping scheme that enables receivers to demonstrate high performance in wireless fading environments. Called carrier interferometry pulse shaping, pulses are created by the superposition of N carriers. At the receiver, low probability-of-error performance is achieved by breaking the pulse into its frequency components and optimally recombining to create frequency diversity benefits. When implemented in a wireless TDMA system, simulations indicate 5-8-dB improvement at probability-of-error of 10 ^-2 over traditional Gaussian pulse shaping with decision feedback equalization (DFE(6,4)) in hilly terrain (HT) and typical urban (TU) channels     

一种用于背板互连的10 Gbit/s接口电路

基于SMIC 40 nm CMOS工艺,提出了一种用于背板互连的10 Gbit/s I/O接口电路。该接口电路由前馈均衡器(FFE)、接收机前端放大器和判决反馈均衡器(DFE)组成。FFE对发射端信号进行预加重,DFE消除较大的残余码间干扰。重点分析了FFE和DFE在消除码间干扰时存在的问题。使用改进的FFE减少对发射端信号的衰减,保证信号到达接收端时具有较大幅度,实现接收机对信号的正确判决,降低系统的误码率。测试结果表明,系统数据率为10 Gbit/s,传输信道在Nyquist频率(即5 GHz)处的衰减为22.4 dB。在1.1 V电源电压下,判决器Slicer输入端信号眼图的眼高为198 mV,眼宽为83 ps。FFE的功耗为31 mW,接收机前端放大器的功耗为1.8 mW,DFE的功耗为5.4 mW。     

A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter

A 4-bit 6-GS/s pipeline A/D converter with 10-way time-interleaving is demonstrated in a 0.18-/spl mu/m CMOS technology. The A/D converter is designed for a serial-link receiver and features an embedded adjustable single-tap DFE for channel equalization. The ISI subtraction of the DFE is performed at the output of each pipeline stage; hence the effective feedback delay requirement is relaxed by 6/spl times/. Code-overlapping of the 1.5-bit pipeline stage along with digital error correction is used to absorb and remove the remainder of the ISI. The measured A/D converter performance at 6-GSamples/s shows 22.5 dB of low-frequency input SNDR for the calibrated A/D converter with /spl plusmn/0.25 LSB and /spl plusmn/0.4 LSB of INL and DNL, respectively. The input capacitance is 170 fF for each A/D converter. The DFE tap coefficient is adjustable from 0 to 0.25 with 6-bits of programmable weight. With a DFE coefficient of 0.2, the measured DFE performance shows 2.5 dB of amplitude boosting for a 3-GHz input sinusoid. The 1.8/spl times/1.6 mm/sup 2/ chip consumes 780 mW of power from a 1.8-V power supply.     

Comparison of DFE and MLSE Receiver Performance on HF Channels

Data communication at rates near or above 2 kbits/s on 3 kHz-baadwidth HF radio channels is subject to impairment from severe linear dispersion, rapid channel time variation, and severe fading. In this investigation, recorded 2.4 kbit/s QPSK signals received from HF channels were processed to extract a time-varying estimate of the channel impulse response. From the estimated channel impulse responses, performance-related parameters were computed for ideal matched filter reception, maximum-likelihood sequence-estimation (MLSE), and decision feedback equalization (DFE). The results indicated that the simpler DFE receiver suffered only a small theoretical performance degradation relative to the more complex MLSE receiver. Other HF channel impulse response statistics were also obtained to shed light on equalization and filter adaptation techniques.     

A 10 Gb/s receiver with half rate period calibration CDR and CTLE/DFE combiner

This paper presents the design of a 10 Gb/s low power wire-line receiver in the 65 nm CMOS process with 1 V supply voltage.The receiver occupies 300×500/μm2.With the novel half rate period calibration clock data recovery(CDR)circuit,the receiver consumes 52 mW power.The receiver can compensate a wide range of channel loss by combining the low power wideband programmable continuous time linear equalizer(CTLE)and decision feedback equalizer(DFE).     

A nonlinear electrical equalizer with decision feedback for OOK optical communication systems

In this paper we introduce a nonlinear equalizer using the Radial Basis Function (RBF) network with decision feedback equalizer (DFE) for electronic dispersion compensation in optical communication systems with on-off-keying and a direct detection receiver. The RBF method introduces a non-linear equalization technique suitable for optical communication direct detection systems that include nonlinear transformation at the photodetector. A bit error rate performance comparison shows that the RBF with DFE out performs the RBF without DFE and achieves similar results provided by maximum likelihood sequence estimator.