A Clinical Application of Ensemble ICA to the Quantification of Myocardial Blood Flow in Dynamic H152 O H^{{15}}_{2} O PET

Ensemble independent component analysis (ICA) is a Bayesian multivariate data analysis method which allows various prior distributions for parameters and latent variables, leading to flexible data fitting. In this paper we apply ensemble ICA with a rectified Gaussian prior to dynamic positron emission tomography (PET) image data, emphasizing its clinical usefulness by showing that major cardiac components are successfully extracted in an unsupervised manner and myocardial blood flow can be estimated in 15 among 20 patients. Detailed experiments and results are illustrated.

A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over \mathbb{F}_{{2^{{163}} }} using Gaussian Normal Bases

This paper presents a comprehensive analysis of the design of custom instructions in a reconfigurable hardware platform dedicated to accelerate arithmetic operations in the binary field $\mathbb{F}_{{2^{{163}} }} $ , using a Gaussian normal basis representation. The resulting platform is capable of running real applications, thus allowing a precise measurement of the execution overheads, and a fair comparison of the hardware and software speedups at several implementation levels. By using this approach, we determine which field operations (e.g., multiplication) are better suited to constrained environments, and which ones provide an enhanced performance in general-purpose systems. Experimental results reveal that by using our fastest field multiplier implemented as a custom instruction in a combined hardware/software approach, we accelerate point multiplication (the fundamental operation in Elliptic Curve Cryptography) over 126 times.     

Parallel Memory Architecture for Elliptic Curve Cryptography over $$ \mathbb{G}\mathbb{F}{\left( p \right)} $$ Aimed at Efficient FPGA Implementation

Parallelization of operations is of utmost importance for efficient implementation of Public Key Cryptography algorithms. Starting with a classification of parallelization methods at different abstraction levels of public key algorithms, we propose a novel memory architecture for elliptic curve implementations with multiple modular multiplier units. This architecture is well-suited for different point addition and doubling algorithms over to be implemented on FPGAs. It allows the execution time to scale with the number of modular multipliers and exhibits nearly no overhead compared to the mere runtime of the multipliers. The advantages of this distributed memory architecture are demonstrated by means of two different point addition and doubling algorithms.

Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile Devices

Elliptic curve cryptography (ECC) is recognized as a fast cryptography system and has many applications in security systems. In this paper, a novel sharing scheme is proposed to significantly reduce the number of field multiplications and the usage of lookup tables, providing high speed operations for both hardware and software realizations.

Some New Expressions for Nakagami Fading Based on Order Statistics

Alternative representations based on order statistics are derived for the probability of error for orthogonal, biorthogonal, and transorthogonal signaling. Short programs in are developed for the computation of these representations and to furnish evidence to show that their performance is superior to the traditional Monte Carlo approach.

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN

In an orthogonal frequency division multiplexing-based wireless local area network receiver there are three operations that can be performed by a unique coordinate rotation digital computer (CORDIC) processor since they are needed in different time instants. These are the rotation of a vector, the computation of the angle of a vector and the computation of the reciprocal. This paper proposes a common architecture of CORDIC algorithm suitable to implement the three operations with a reduced increase of the hardware cost with respect to a single operation CORDIC. The proposed architecture has been validated on field programmable gate-arrays devices and the results of the implementation show that area saving around 28% and throughput increment of 64% are obtained.

Scheduling for information gathering on sensor network

We investigate a unique wireless sensor network scheduling problem in which all nodes in a cluster send exactly one packet to a designated sink node in an effort to minimize transmission time. However, node transmissions must be sufficiently isolated either in time or in space to avoid collisions. The problem is formulated and solved via graph representation. We prove that an optimal transmission schedule can be obtained efficiently through a pipeline-like schedule when the underlying topology is either line or tree. The minimum time required for a line or tree topology with nodes is . We further prove that our scheduling problem is NP-hard for general graphs. We propose a heuristic algorithm for general graphs. Our heuristic tries to schedule as many independent segments as possible to increase the degree of parallel transmissions. This algorithm is compared to an RTS/CTS based distributed algorithm. Preliminary simulated results indicate that our heuristic algorithm outperforms the RTS/CTS based distributed algorithm (up to 30%) and exhibits stable behavior.

Overall Requirements for Global Information Multimedia Communication Village <Emphasis Type="Italic">10th Strategic Workshop</Emphasis>

The foundations for the definition of the network of the future should be based on a correct user and community characterizations to minimize the fragmentation of the experiences during the global interactions with information communication infrastructures. This paper describes some of the complex objectives and main challenges that telecommunication solution and services have to deal with in order to respect both specific requirements of global user interactions, habits and personalization, and framework requirements about green environments.

Real-time resource allocation for LEO satellite constellations

The paper addresses the need of controling the access of terminals with guaranteed ressources on the high dynamic systems offered by LEO satellite constellations. A call-access-control scheme that guarantees the reservation of permanent resources of satellite constellations in $O(\sqrt(n)\hbox{log}(n))The paper addresses the need of controling the access of terminals with guaranteed ressources on the high dynamic systems offered by LEO satellite constellations. A call-access-control scheme that guarantees the reservation of permanent resources of satellite constellations in time, where n is the number of user present in the system, is described. A tradeoff between computational time of call-access-control and optimization of the use of the spectrum is identified. Some experimental results are presented.

Jér?me GaltierEmail:

     

A Survey of Cryptographic Primitives and Implementations for Hardware-Constrained Sensor Network Nodes

In a wireless sensor network environment, a sensor node is extremely constrained in terms of hardware due to factors such as maximizing lifetime and minimizing physical size and overall cost. Nevertheless, these nodes must be able to run cryptographic operations based on primitives such as hash functions, symmetric encryption and public key cryptography in order to allow the creation of secure services. Our objective in this paper is to survey how the existing research-based and commercial-based sensor nodes are suitable for this purpose, analyzing how the hardware can influence the provision of the primitives and how software implementations tackles the task of implementing instances of those primitives. As a result, it will be possible to evaluate the influence of provision of security in the protocols and applications/scenarios where sensors can be used.

An Efficient Hillclimbing-based Watershed Algorithm and its Prototype Hardware Architecture

Image segmentation is the process of isolating objects in an input image, that is, partitioning the image into disjoint regions, such that each region is homogeneous with respect to some property, such as gray value or texture. Watershed-based image segmentation has gained much popularity in the field of biomedical image processing and computer vision where large images are not uncommon. Time-critical applications like road traffic monitoring, and steel fissure analysis require fast realization of the segmentation results. The present paper proposes a fast watershed transform based on hillclimbing technique. The complexity of the algorithm has been reduced by doing away with multiplication normally required to form a lower complete image in an intermediate step of the overall segmentation. The reduced complexity makes the algorithm suitable for dedicated hardware implementation. An FPGA-based architecture has been developed to implement the proposed algorithm involving moderate hardware complexity. This architecture enhances the applicability of this algorithm for real-time applications.

Biosequence Similarity Search on the Mercury System

Biosequence similarity search is an important application in modern molecular biology. Search algorithms aim to identify sets of sequences whose extensional similarity suggests a common evolutionary origin or function. The most widely used similarity search tool for biosequences is BLAST, a program designed to compare query sequences to a database. Here, we present the design of BLASTN, the version of BLAST that searches DNA sequences, on the Mercury system, an architecture that supports high-volume, high-throughput data movement off a data store and into reconfigurable hardware. An important component of application deployment on the Mercury system is the functional decomposition of the application onto both the reconfigurable hardware and the traditional processor. Both the Mercury BLASTN application design and its performance analysis are described.

A State-of-the-art Elliptic Curve Cryptographic Processor Operating in the Frequency Domain

We propose a novel area/time efficient elliptic curve cryptography (ECC) processor architecture which performs all finite field arithmetic operations in the discrete Fourier domain. The proposed architecture utilizes a class of optimal extension fields (OEF) GF(q ^m ) where the field characteristic is a Mersenne prime q = 2 ⁿ  − 1 and m = n. The main advantage of our architecture is that it achieves extension field modular multiplication in the discrete Fourier domain with only a linear number of base field GF(q) multiplications in addition to a quadratic number of simpler operations such as addition and bitwise rotation. We achieve an area between 25k and 50k equivalent gates for the implementations over OEFs of size 169, 289 and 361 bits. With its low area and high speed, the proposed architecture is well suited for ECC in small device environments such as sensor networks. The work at hand presents the first hardware implementation of a frequency domain multiplier suitable for ECC and the first hardware implementation of ECC in the frequency domain.

A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC

This paper presents a compact hardware architecture of Context-Based Adaptive Binary Arithmetic Coding (CABAC) codec for H.264/AVC. The similarities between encoding algorithm and decoding algorithm are explored to achieve remarkable hardware reuse. System-level hardware/software partition is conducted to improve overall performance. Meanwhile, the characteristics of CABAC algorithm are utilized to implement dynamic pipeline scheme, which increases the processing throughput with very small hardware overhead. Proposed architecture is implemented under 0.18 μm technology. Results show that the core area of proposed design is 0.496 mm² when the maximum clock frequency is 230 MHz. It is estimated that the proposed architecture can support CABAC encoding or decoding for HD1080i resolution at a speed of 30 frame/s.

High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function

High-speed and low area hardware architectures of the Whirlpool hash function are presented in this paper. A full Look-up Table (LUT) based design is shown to be the fastest method by which to implement the non-linear layer of the algorithm in terms of logic. An unrolled Whirlpool architecture implemented on the Virtex XC4VLX100 device achieves a throughput of 4.9 Gbps. This is faster than a SHA-512 design implemented on the same device and other previously reported hash function architectures. A low area iterative architecture, which utilises 64-bit operations as opposed to full 512-bit operations, is also described. It runs at 430 Mbps and occupies 709 slices on a Virtex X4VLX15. This proves to be one of the smallest 512-bit hash function architectures currently available.

Error Probability for <Emphasis Type="Italic">L</Emphasis>-branch Coherent BPSK Equal Gain Combiners over Generalized Rayleigh Fading Channels

In this paper, a closed-form expression for the probability of error in a coherent BPSK system over Generalized Rayleigh fading channels is derived. An L-branch equal gain combining diversity scheme is used. Theoretical results for the probability of error are plotted for various values of the number of degrees of freedom (n) and diversity order (L). A simulation is performed and the simulated results are found to match very well with the theoretical results.

Finite-state Markov Model for Lognormal,Chi-square (Central), Chi-square (Non-central), and <Emphasis Type="Italic">K</Emphasis>-distributions

This paper formulates a finite-state Markov channel model to represent received signal-to-noise (SNR) ratios having lognormal, K-distribution, chi-square (central) and chi-square (non-central) distributions in a slow fading channel. The range of the SNRs is partitioned into a finite number of states following earlier works in literature. Performance measures like level crossing rates, steady-state probabilities, transition probabilities, and state-time durations are derived, and numerical results are plotted and discussed for the FSMC models for all the distributions.

MGFs for Rayleigh Random Variables

Expressions are given for the moment generating functions of the Rayleigh and generalized Rayleigh distributions.