Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

MOS switched-capacitor filters

In the past several years, much progress has been made in bringing the economies of integrated-circuit technology to bear on the realization of voiceband frequency selective filters. This paper will review one approach to this problem, the use of switched-capacitor techniques. The paper emphasizes the practical aspects of switched-capacitor filter design under the constraints imposed by MOS integrated-circuit technology. The basic operation of switched-capacitor filters is reviewed, followed by a discussion of the properties of the various circuit building blocks in MOS technology. Finally, a summary of several filter organizations which appear to be well suited to switched-capacitor implementation is presented.     

Testable switched-capacitor filters

A design-for-testability (DFT) methodology for switched-capacitor (SC) filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and online test. A programmable biquad is used for on-chip comparison of the transfer functions for every filter stage. Test area overhead consists of the programmable biquad, a set of switches, and a finite-sequential-machine (FSM) control part. The design and implementation of an example filter are included to assess the potential usefulness of this approach     

New switched-capacitor ladder filters

A method is described and implemented for the derivation of switched-capacitor discrete-time filters from analogue passive filters of the ladder doubly terminated kind. The method is based on linear transformation active (LTA) synthesis, and yields some very interesting results.     

Pseudopower in switched-capacitor filters

The concepts of pseudopower, pseudopassivity, and pseudolosslessness are introduced in connection with switched-capacitor filters employing voltage invertor switches. With such concepts the verification of the low sensitivity and stability properties is straightforward.     

Offset-compensated switched-capacitor leapfrog filters

Offset-compensated SC leapfrog filters can be realised as shown in the letter. The filters are parasitic-insensitive and the switches are controlled by a 3-phase clock. A 5th-order lowpass filter is given as an example.     

Parasitics-insensitive switched-capacitor ladder filters

A simple method for designing parasitics-insensitive switched-capacitor (s.c.) ladder filters is described. The response of the s.c. filter is related to that of a continuous-time prototype circuit by the bilinear z-transform.     

Increasing the clock frequency of switched-capacitor filters

The time constant ? of a switched-capacitor (s.c.) integrator is C/(fcCR), where CR is the value of the s.c., C the integrating capacitor and fc the clock frequency. For a given ?, if fc is to increase, C/CR must increase proportionately. Since a large capacitor ratio C/CR is inconvenient to implement in an integrated circuit, most s.c. filters are clocked at the Nyquist rate. Since higher clock rates reduce switching delays, a technique of enabling higher clock frequencies without the need for large capacitor ratios has been developed.     

Design for testability and DC test of switched-capacitor circuits

The authors present a design for testability (DFT) technique for switched-capacitor circuits. The principle is to reconfigure the SC circuit so that it realises a cascade of DC voltage amplifiers in which all capacitors are represented in a simple form. Then, the transfer function becomes a product of the ratio of two capacitors and the sensibility of the DC gain to each capacitor is close to unity. Consequently, a simple test with partial diagnosis is realised with some DC voltage stimuli and gives an accurate test result at the output of the last voltage amplifier     

Stability test for switched-capacitor filters

A general stability test is described which may be employed in the analysis of all switched-capacitor filters of the lossless discrete integrator (LDI) type.     

Alternative approach to the design of switched-capacitor filters

An alternative switched-capacitor filter design is shown to be possible using an economic form of c.c.d. A simple example of a biquadratic digital-filter section is included to illustrate the point. This leads to comment on the relationship between switched-capacitor filters, the N-path filter and the digital filter.     

CMOS high-frequency switched-capacitor filters fortelecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use in a switched digital video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84 MHz (f_s =2f_clock=103.68 MHz for double sampling) while the three desired low-pass corner frequencies (f_c) are 8,12, and 20 MHz. The double-sampling, bilinear, elliptic, fifth-order switched-capacitor filter meets the desired -40-dB attenuation at 1.3 f _c, and -30 dB at 1.25 f_c. For the 12-MHz corner frequency setting, given the 2V_pp differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB. The analog power dissipation is 125 mW from a 5-V power supply. The test results indicate that the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype IC's are fabricated in a 0.35-μm 5-V (0.48 μm drawn) CMOS process     

Synthesis of highpass switched-capacitor LDI filters

Exact techniques are given for the design of highpass LDI switched-capacitor ladder filters. The filters have no lumped counterparts and cannot be obtained from a lumped prototype by a transformation. Only stray-insensitive circuits are employed in the realisation, and the filters retain the lowsensitivity properties of a passive (distributed) prototype function.     

Reduction of finite-gain effect in switched-capacitor filters

A simple technique for significantly reducing the effect of the finite gain of amplifiers on the performance of switched-capacitor filters is presented. The effectiveness of this technique has been established by extensive simulation studies. This technique has the potential for simplifying amplifier design and extending the frequency range of switched-capacitor filters by trading gain for bandwidth.     

Test of switched-capacitor ladder filters using OBT

In this paper, a way to test switched-capacitors ladder filters by means of Oscillation-Based Test (OBT) methodology is proposed. Third-order low-pass Butterworth and Elliptic filters are considered in order to prove the feasibility of the proposed approach. A topology with a non-linear element in an additional feedback loop is employed for converting the Circuit Under Test (CUT) into an oscillator. The idea is inspired in some author's previous works (G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Oscillation-based Test Experiments in Filters: a DTMF example, in: Proceedings of the International Mixed-Signal Testing Workshop (IMSTW'99), British Columbia, Canada, 1999, pp. 249–254; G. Huertas, D. Vazquez, E. Peralías, A. Rueda, J.L. Huertas, Oscillation-based test in oversampling A/D converters, Microelectronic Journal 33(10) (2002) 799–806; G. Huertas, D. Vázquez, E. Peralías, A. Rueda. J.L. Huertas, Oscillation-based test in bandpass oversampled A/D converters, in: Proceedings of the International Mixed-Signal Test Workshop, June 2002, Montreaux (Switzerland), pp. 39–48; G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Practical oscillation-based test of integrated filters, IEEE Design and Test of Computers 19(6) (2002) 64–72; G. Huertas, D. Vázquez, E. Peralías, A. Rueda, J.L. Huertas, Testing mixed-signal cores: practical oscillation-based test in an analog macrocell, IEEE Design and Test of Computers 19(6) (2002) 73–82). Two methods are used, the describing function approach for the treatment of the non linearity and the root-locus method for analysing the circuit and predicting the oscillation frequency and the oscillation amplitude. In order to establish the accuracy of these predictions, the oscillators have been implemented in SWITCAP (K. Suyama, S.C. Fang, Users' Manual for SWITCAP2 Version 1.1, Columbia University, New York, 1992). Results of a catastrophic fault injection in switches and capacitors of the filter structure are reported. A specification-driven fault list for capacitors is also defined based on the sensitivity analysis. The ability of OBT for detecting this kind of faults is presented.     

Exact design of switched-capacitor bandpass ladder filters

An exact design of switched-capacitor bandpass filters is presented. This new technique is based on the distributed circuit theory with a suitable bandpass transformation. The theoretical aspects of this method are given as well as the simulated results using a switched-capacitor circuit-analysis program.     

Power-supply rejection in differential switched-capacitor filters

The principal motivation of using a fully differential configuration is to reduce power supply coupling. For this reason, an analysis of some of the mechanisms associated with this effect and the usefulness of some forms of common mode feedback are discussed. Experimental results obtained from a CMOS integrated circuit realization are also included. The circuit achieves 50 dB of power supply rejection ratio across the passband.     

Ladder-simulation switched-capacitor filters with inductor loops

In ladder-simulation switched-capacitor filters, offset voltages of the op-amps can cause the output simulating inductor currents to build up if the LC prototype contains an inductor loop. This problem is eliminated by a novel technique where the sum of inductor currents flowing into each node is simulated by one op-amp output.     

A single-chip codec with switched-capacitor filters

A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.     

Parasitics-compensated building blocks for switched-capacitor filters

A switched-capacitor voltage-controlled charge source with differential outputs and a switched-capacitor differential integrator are proposed. The proposed circuits are parasitics insensitive, and can be operated using only a two-phase clock.