以太网知识讲座(2)——以太网介质接入控制方法和物理层性能标准规范

系统地介绍了以太网的基本概念，介质接入控制和物理层标准规范，以太网信号的帧结构，网络硬件设备，网络组成及主要的性能，以及以太网信号在PDH，SDH／SONET中的传输等等，本部分为介质接入控制方法和物理层性能的标准规范，在介质接入控制方法方面介绍耻半双工和全双工以太网两种工作模式，在物理层性能标准规范方面分别介绍了1Mbit/s,10Mbit/s,100Mbit/s,1000Mbit/s以太网的物理层性能标准规范。     

新品展馆

无线网关Bluesocket公司专为各种网络环境的大型企业应用所设计的WG-5000无线网关,是一种高性能的WLAN基础设施平台,通常部署在网络核心或分配层,可聚集从现有边缘交换机进入安全企业网的WLAN业务。它可部署符合规定方针的增强型WLAN,并按照任务、时间、位置、业务或用户的不同,控制接入、带宽和QoS。该设备硬件的特点是2个10/100/1000Mbit/s接口(另加failover),以及可选的1000Base-SX光纤接口和固态存储。该网关支持数百个接入点和多达1000个用户同时使用,并具有高性能1Gbit/s未加密和400Mbit/s加密的通过量。通用接入点SMCNetw…     

0.18μm CMOS, Monolithic MSTP ASIC

I. Introduction Motivated by adopting both telecom and data-com traffic into Synchronous Digital Hierarchy (SDH)[1] transport payloads, we develop the mono-lithic Multi-Service Transport Platform (MSTP)[2] Application Specified Integrated Circuit (ASIC) MSEOSX8-6, which is a highly integrated device capable of mapping 10/100/1000Mbit/s Ethernet[3], 155Mbit/s Resilient Packet Ring (RPR)[4], as well as 2.048Mbit/s E1 traffic into SDH STM-1 payloads. On the line side, the chip s…     

1.5 Mbit/s高压缩率编码方式

众所周知,电视会议、电视电话等图象信号的传输频带大约是电话传输频带的1000倍,因此它的传输成本很高。为了降低传输费用和普及电视会议和电视电话业务,压缩图象信号的传输频带便成为一个重要的研究课题。最近,日本电报电话公司电信研究所在原来32Mbit/s和6.3Mbit/s两种频带压缩编码基础上,研究成功一种高压缩率的1.5Mbit/s图象信号编码传输方式。32Mbit/s压缩编码传输方式是在一幅图象画面内利用相邻画面间连接处的相同部分,取其不同部分的信号进行     

基于DSP的10Mbit／s共享以太网络设计

文章通过设计DSP芯片TMS32 0F2 0 6与具有ISA总线接口的 10Mbit/s以太网络控制器RTL80 19AS的软、硬件接口 ,实现了基于DSP的 10Mbit/s共享以太网络结构     

锐捷网络NEP出口引擎新品 轻松化解网络出品拥塞难题

近日，锐捷网络针对网络出口的应用需求推出了一款令人震惊的全新产品——NPE50网络出口引擎。它无论在产品性能还是在功能特性方面都具有划时代的意义。随着网络的飞速发展，国内IP地址资源已经匮乏，NAT成为网络出口设备的必备功能。园区网络规模的不断扩大，出口带宽也从原来的10Mbit／s、100Mbit／s升级到现在的1000Mbit／s，甚至多个1000Mbit／s出口，     

新一代智能光交换设备--OPTera Connect HDX

1 HDX是面向光网络市场需求的新产品 近几年,中国电信、中国网通、中国移动、中国联通和铁通公司都已经或正在建设各自的骨干传输网和大容量城域网,网络设计的业务颗粒已从过去的2 Mbit/s上升为155 Mbit/s、622 Mbit/s甚至更高.2.5 Gbit/s和10 Gbit/s的SDH设备已大量应用于骨干网和大城市城域网上.     

多载波HSPA＋部署量猛增 不同制式网络差距拉大

在LTE大势下,HSPA＋在提升移动宽带用户体验上仍有巨大的空间。MIMO（多输入输出）、双载波的应用使HSPA＋历经了21Mbit/s、28Mbit/s、42Mbit/s,产业链在21 Mbit/s HSPA＋引入了下行64QAM高阶调制技术、在28Mbit/s阶段引入了MIMO技术后,爱立信、华为、中兴、诺基亚西门子通信等占据HSPA＋市场主要份额的设备巨头又在42Mbit/s阶段则引入了DC（双载波）技术,实现了84Mbit/s这一峰值速率,甚至以四载波方式将HSPA＋带入了112Mbit/s这一历史新高度,明显提升了HSPA＋网络在体系吞吐量、单用户体验、频谱利用率等方面的性能。随之迅速增长的,是今年前三季度的全球运营商双载波HSPA＋网络数量。     

8端口ATM工作组交换机设计与性能分析

本文概述了基于FPGA的8端口155Mbit/s(25Mbit/s)ATM工作组交换机的设计,对其关键部分如输入输出端口处理,交换结构等进行了阐述,并对其性能进行了分析,试验运行表明各项指标均满足设计要求。     

罗马尼亚Cosmote计划2014年4G网络覆盖扩大至160个城市

近日,罗马尼亚运营商Cosmote 公司表示,计划在2014年将其4G LTE 网络覆盖范围扩大至超过160个城镇和城市。2013年4月底,Cosmote宣布在布加勒斯特、欧特佩尼等地推出LTE商用服务,使用户体验到最高达75/37.5 Mbit/s (下行/上行）的网速。Cosmote还在罗马尼亚159个城市和超过1000个地点提供双载波HSPA+服务,网速高达43.2 Mbit/s。此外,该运营商还在189个城市提供21.6 Mbit/s的HSPA+服务,使其3G网络覆盖了73%的罗马尼亚人口。     

Space optical communications with the Nd: YAG laser

The development of a Nd : YAG space laser communication system is discussed with respect to history, potential applications, and present status. The basic design of an Air Force Space Communications Flight Test operable at a data rate of 1000 Mbit/s is described at both the system and component level. An engineering feasibility model of this system has been completed, and the results of tests data are reported. Communications at 1000 Mbit/s with a receiver sensitivity of 20 photoelectrons/bit was demonstrated for a bit error rate of 10^-6, interterminal tracking with angle erros less than 1 µrad, and station to station acquisition in less than 6 s. A simulated range of 40 000 km was used.     

基于PCI-Express的千兆以太网控制芯片的设计

介绍了采用0.13微米工艺设计的高集成度1000Base-T千兆以太网传输控制器芯片。主要模块包括1000Base-T物理层收发器,数据链路层控制器,高性能DMA控制器和目前最先进的第三代PC接口PCI-Express。     

AX88180在嵌入式系统中的应用

AX88180是一款高性能低成本的Non-PCI千兆以太网控制器,适用于多种需要高速接入网络的嵌入式系统,如消费电子和家庭网络等.AX88180内置10/100/1000 Mb/s以太网媒体存取控制器(MAC),符合IEEE 802.3/IEEE 802.3u/IEEE 802.3ab协议,可与一般16/32位微控制器连接,其操作与SRAM相同.介绍了AX88180的原理与特性,并给出了具体的应用电路.     

IsoEthernet: an integrated services LAN

IsoEthernet is an integrated services LAN directed at multimedia applications. It enables the carrying of 6.144 Mb/s of isochronous data (96 B-channels at 64 kb/s each) in addition to 19 Mb/s of 10Base-T traffic using the existing 10Base-T wiring infrastructure. A 10Base-T mode of operation accommodates existing 10Base-T equipment. Interoperability with 10Base-T networks is provided for packet traffic. IsoEthernet is being standardized by the IEEE 802.9 standards committee     

基于MPC8280的PCI驱动设计

芯片MPC8280的主频最高为450 MHz,仅靠运行在其上的软件虽可实现路由交换功能,但交换容量仅约为40 Mbit·s-1,无法满足多路千兆交换性能要求。利用MPC8280的PCI口外接千兆交换芯片BCM56514,能突破这一性能瓶颈。基于MPC8280的PCI驱动,使得MPC8280通过PCI 内存空间读写操作、配置空间读写操作和I/O空间的读写操作,并实现对BCM56514的配置、控制及路由表的更新,从而使MPC8280在路由交换领域得以应用。     

565Mbit／s光中继器插分方式

本文叙述了565Mbit/s光中继器插分方式,并进行了计算机电路模拟和实验。     

Design of integrated services digital broadcasting systems usingmultirate optical fiber code-division multiplexing

This paper presents the design of a new type of integrated services digital broadcasting (ISDB) systems which use a multirate optical fiber code-division multiplexing (OF-CDM) technique. The proposed system can efficiently multiplex various kinds of digital signals with multiple bit rates. This is feasibly achieved by using strict optical orthogonal codes of both auto- and cross-correlation constraints being “1” in multirate OF-CDM systems. Moreover, the low-cost design of OF-CDM transmitters is presented, and experimental demonstrations are also carried out. The measured results show that a transmission distance up to 13 km can be feasibly accomplished by using the proposed transmitter design and the external optical injection-locking scheme. It is expected that the proposed ISDB systems can be employed to cost-effectively transmit fast ethernet (125 Mbit/s), FDDI (125 Mbit/s), ATM (155 Mbit/s), and ESCON (200 Mbit/s) protocol data. Their potential applications include Internet services and multimedia broadcasting, such as videoconferencing, video on demand, HDTV, distance learning, and World Wide Web     

Reconfigurable design and implementation of the MD6 Hash function

Efficient reconfigurable field programmable gate array (FPGA) architectures for the MD6-224/256/384/512 Hash algorithm are proposed in this article. The basic iterative compact design requires 923 ALMs and achieves a throughput ranging from 225 Mbit/s to 394 Mbit/s at a maximum frequency of 198 MHz. The 32-step-unrolled high-throughput design requires 7 090 ALMs and achieves a throughput ranges from 5 776 Mbit/s to 9 490 Mbit/s at a maximum frequency of 173 MHz. The simulation results show that high flexibility and efficient FPGA implementation of the MD6 Hash function is achieved.     

1 Gbit/s high-speed bit-synchronisation LSI for B-ISDN

The CCITT recommended that the bit rates for synchronous digital hierarchy (SDH) should be multiples of 155.52 Mbit/s. In handling high-speed data (such as 622.08 Mbit/s) in B-ISDN switching systems, there are problems associated with waveform degradation caused by impedance mismatching and amplitude attenuation. A countermeasure is the regeneration of the distorted waveforms using the system clock in each board. A bit-synchronisation circuit allows distorted waveforms to be regenerated and simplifies the design of timing between boards. The author have developed a high-speed bit-synchronisation LSI with excellent jitter tolerance in the 600 Mbit/s region and which has a simple circuit structure. The LSI features a circuit structure based on an elastic store, Si-bipolar super self-aligned process technology (SST),/sup 1/ and careful timing design. It can handle three different bit-rates (622.08, 155.52, and 51.84 Mbit/s) and has a maximum bit rate of 1 Gbit/s.<>