136-MHz/400-MHz radio-sky maps

A radio-sky map, covering the whole celestial sphere, is helpful for determining the system noise temperature of an earth-based satellite receiving system. Detailed sky maps for the 136- and 400-MHz space research (space-to-earth) satellite frequency bands have been generated, using a computer, by the National Aeronautics and Space Administration (NASA).     

Integrated Low-Jitter 400-MHz Femtosecond Waveguide Laser

An integrated passively mode-locked waveguide laser generating 440-fs pulses at 394-MHz repetition rate is demonstrated on an 18 mm $, times ,$44 mm silica waveguide chip. The laser self-starts, and uses a saturable Bragg reflector for mode-locking.      

A 400-MHz S/390 microprocessor

A microprocessor implementing IBM S/390 architecture operates in a 10+2 way system at frequencies up to 411 MHz (2.43 ns). The chip is fabricated in a 0.2-μm L_eff CMOS technology with five layers of metal and tungsten local interconnect. The chip size is 17.35 mm×17.30 mm with about 7.8 million transistors. The power supply is 2.5 V and measured power dissipation at 300 MHz is 37 W. The microprocessor features two instruction units (IUs), two fixed point units (FXUs), two floating point units (FPUs), a buffer control element (BCE) with a unified 64-KB L1 cache, and a register unit (RU). The microprocessor dispatches one instruction per cycle. The dual-instruction, fixed, and floating point units are used to check each other to increase reliability and not for improved performance. A phase-locked-loop (PLL) provides a processor clock that runs at 2× the system bus frequency. High-frequency operation was achieved through careful static circuit design and timing optimization, along with limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. Timing-driven synthesis and placement of the control logic provided the maximum flexibility with minimum turnaround time. Extensive use of self-resetting CMOS (SRCMOS) circuits in the on-chip L1 cache provides a 2.0-ns access time and up to 500 MHz operation     

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronousmirror delay

A 256-Mb SDRAM (245.7 mm²) has been developed using (1) a high cell occupation ratio (60.2%) array design for chip size reduction and a high yield, (2) a prefetched pipeline scheme (PPS) using a first-in first-out (FIFO) buffer with parallel serial converter for 250-MHz clock frequency operation, and (3) a synchronous mirror delay (SMD) circuit for 2.5-ns clock access and low standby current     

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

We have used a 5-metal 0.18-μm CMOS logic process to develop a 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. The macro contains: (1) end-point dual-pulse drivers for accurate timing control; (2) a wordline-voltage-level compensation circuit for stable data retention; and (3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also developed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CMOS process using 0.13-μm gate length     

A 50-MHz 8-Mbit video RAM with a column direction drive senseamplifier

An 8-Mb (1-Mwords×8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7-μm n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8×3.0 μm², and the chip area is 12.7×16.91 mm²     

A 400-MHz DA converter with a 4-bit color map for 2000-line display

A video digital-to-analog (DA) converter with a color map is discussed that is monolithic, bipolar, and achieves ultrahigh speed. When the chip is addressed with 4-bit video data, 256-step color-map data can be used in an extremely high-definition 2000-pixel×2000-pixel display. A combination of two emitter-coupled logic (ECL) RAMs and a data-multiplex DA converter is used. The conversion rate is 400 MHz, the settling time of the DA converter is 2 ns, the rise and fall times are both 0.8 ns, and the power consumption is 1.3 W     

Circuit techniques in a 266-MHz MMX-enabled processor

The AMD-K6 MMX-enabled processor is plug-compatible with the industry-standard Socket 7 and is binary compatible with the existing base of legacy X86 software. The microarchitecture is based on an out-of-order, superscalar execution engine using speculative execution. High performance and compact die size are achieved by using self-resetting, self-timed and pulsed-latch circuit design techniques in custom blocks and placed-and-routed blocks of standard cells. The 162 sq. mm die is fabricated on a 0.35-μm, five-layer metal process with local interconnect. It is assembled into a ceramic pin grid array (PGA) using C4 flip-chip mounting. The processor functions at clock speeds up to 266 MHz     

400-MHz Acoustic Surface-Wave Pulse Expansion and Compression Filter (Correspondence)

An acoustic surface-wave device capable of both the generation and compression of a linear FM waveform has been developed. The device has a synchronous frequency of 400 MHz, a dispersive bandwidth of 80 MHz, and achieved a pulse compression ratio of 25:1. The uncompressed pulsewidth is 0.5 /spl mu/s.     

Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator

The paper presents a switched-current circuit implementation of a chaotic algorithm to generate a white noise. A 3-bit digital normalizer is utilized to adjust the coefficients in the piecewise-linear transfer function such that the probability of the generated numbers will be very close to a uniform distribution. A 1.0-GHz linear track-and-hold circuit is applied in the random number generator (RNG) to achieve a wide output bandwidth. TSMC 0.25-/spl mu/m one-poly five-metal CMOS process is adopted to carry out the proposed design to verify the wideband performance. When the operating clock is 10.0 MHz, the measured bandwidth of the generated noise is 4.0 MHz.     

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-/spl mu/m DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.     

A 1.0-V 230-MHz column access embedded DRAM for portable MPEGapplications

This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even at 1.0-V power supply condition. The peak power consumption is suppressed to 198 mW in burst operation. The power-down standby mode, which suppresses the leakage current consumption of peripheral circuitry, is also prepared for portable equipment. With the collaboration of array circuit design and the fine Cu metallization technology, macro size of 18.9 mm² and cell efficiency of 51.3% are realized even with dual interface and triple test functions implemented     

A shallow ridged-cavity crossed-slot antenna for the 240- to 400-MHz frequency range

An experimental study has been made of a shallow ridged-cavity crossed-slot antenna to determine its feasibility for operation in the 240- to 400-MHz band. The various trends are summarized for the VSWR response characteristics as the cavity and slot parameters are varied. The wideband antenna characteristics using a ridged cavity configuration are demonstrated. Based on the limited amount of data obtained from the experimental model, the VSWR is < 2.7:1 from 240 to 270 MHz and < 2.1:1 from 290 to 400 MHz for a cavity with a maximum dimension of 33 by 33 by 4 in. Measured radiation patterns with the cavity mounted on a finite-size fiat ground plane are shown.     

A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside asigma-delta modulator loop

A 0.8-μ BiCMOS, 400-MHz intermediate-frequency digitizer based on embedding a down-conversion mixer inside a sigma-delta modulator together with a reconstruction filter in the feedback path has been developed. The digitizer, when subsampled with a clock of 20 MHz, achieves a measured resolution of 12 bits for a 40-kHz bandwidth and dissipates 18 mW of power. The third harmonic distortion (HD₃) is less than -90 dBc for a -4-dB input, and the third-order intermodulation product (IM₃) is less than -70 dBc for a -8-dB input, with a full-scale voltage of 0.5 V. The chip area is 1.5 mm²     

3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

A quasi-complementary BiCMOS gate for low-voltage supply is applied to a 3.3V RISC data path. For a parallel RISC processor, the major issues are the construction of arithmetic modules in a small number of transistors and the shortening of the cycle time as well as the delay time. The feedbacked massive-input logic (FML) concept is proposed to meet these requirements. It reduces the number of transistors and the power within the framework of fully static logic 3-4 times. A low-voltage BiCMOS D-flip-flop is also conceived to allow the single-phase clocking scheme, which is favorable for high-frequency operation of RISCs. To demonstrate these circuit techniques, a 32-b ALU is designed and fabricated using 0.3-μm BiCMOS to demonstrate 1.6 times performance leverage over CMOS at 3.3 V     

使用Verilog实现基于FPGA的SDRAM控制器

介绍了SDRAM的特点和工作原理，提出了一种基于FPGA的SDRAM控制器的设计方法，使用该方法实现的控制器可非常方便地对SDRAM进行控制。     

A 400-MHz random-cycle dual-port interleaved DRAM (D/sup 2/RAM) with standard CMOS Process

This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro exploits three key technologies: fully sense-signal-loss compensating technology based on the whole detailed noise element breakdowns, the novel striped trench capacitor (STC) cell, and the write-before-sensing (WBS) circuit by decoded write-bus. A 400-MHz random cycle access has been verified for D/sup 2/RAM fabricated by a 0.15-/spl mu/m standard CMOS process.     

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor

This paper describes 3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. The processor is implemented in a 0.5-μm BiCMOS technology with 4-metal-layer structure. The chip includes a 240 MFLOPS fully pipelined 64-b floating point datapath, a 240-MIPS integer datapath, and 24 KB cache, and contains 2.8 million transistors. The processor executes up to four operations at 120 MHz and dissipates 17 W. Novel BiCMOS circuits, such as a 0.6-ns single-ended common base sense amplifier, a 0.46-ns 22-b comparator, and a 0.7-ns path logic adder are applied to the processor. The processor with the proposed BiCMOS circuits has a 11%-47% shorter delay time advantage over a CMOS microprocessor     

A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques

A fully differential wideband sixth-order switched-capacitor bandpass filter is designed for channel selection in cable TV applications. A modified double-sampling pseudo-two-path technique is proposed to achieve a second-order wideband bandpass filter with a single opamp. Implemented in a standard double-poly four-metal 0.35-/spl mu/m CMOS process and operated at 176-MHz sampling frequency, the filter achieves a measured center frequency of 44 MHz with a bandwidth of 6.28 MHz and a dynamic range of 58.3 dB at 3% IM3. The filter consumes 92.5mW at a single 3.0-V supply and occupies a chip area of 0.52 mm /sup 2/.     

A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques

A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C/sub IO/ minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.