应用于高Q跨导-电容带通滤波器的线性跨导运放设计

设计了一种具有高的直流增益的宽带线性全差分跨导运放.一方面,并联一个工作在线性区的场效应管来补偿直流三阶系数,得到了一种应用于连续时间滤波器、增加跨导器饱和区输入信号幅度的简单方法.另一方面,结合负电阻电路提高了输出阻抗,实现高的直流增益而不需要额外的内部结点,并减小了因有限直流增益和寄生电容引起的相位偏差.将此全差分跨导运放应用于0.18μmCMOS工艺二阶带通滤波器,在3.3V电源电压、输入峰峰值1V时,HSPICE仿真结果的总谐波失真小于40dB,中心频率为20MHz,3dB带宽为0.18MHz,即Q为110.     

低功耗跨导-电容滤波器及其调谐电路的设计

设计了一种以Nauta跨导为单元结构的5阶切比雪夫跨导-电容带通滤波器及其调谐电路.该电路应用于低中频结构的北斗卫星导航接收机射频前端.滤波器的中心频率为4.092MHz,带宽设计为±2.046 MHz.该滤波器采用锁相环结构的片上自动频率调谐电路,用TSMC0.13 μm RF CMOS工艺实现,芯片面积仅为0.24 mm2,可以在低电压下工作,电路总功耗仅为1.68 mW.     

可调频率跨导电容Chebyshev滤波器的设计及仿真

首先提出了一种新的跨导运放,其输入级采用了工作在线性区的MOS管作源极负反馈有源电阻实现其良好的线性度,输出级采用折叠式结构,并在电路中引入电压共模负反馈(CMFB)稳定其静态工作点。接着提出了一种新的利用开关电容技术调节跨导运放偏置电流值大小的电路,应用该电路可以精确调节跨导运放Gm值的大小,应用这些电路设计得到了四阶Chebyshev低通滤波器,并实现其频率的精确可调,0.35μm2层多晶硅,4层金属CMOS工艺Spicemodel仿真结果表明设计正确、有效。     

中心频率可调的高线性度带通滤波器设计

为了提高滤波器的线性度,文中给出了开关电容电阻不在信号通路中,而将其放在控制电路中的带通滤波器的设计方法。由于该方法采用了特殊的校正技术和匹配技术,因此,该滤波器具有自动调节功能,且其频响曲线随PVT变化在±2kHz内。     

一种高精密的Gm-C 2阶带通滤波器的设计

针对红外接收芯片对带通滤波器参数可调的要求,提出了一种高精密的Gm-C 2阶带通滤波器。该滤波器的中心频率、带宽和通带增益均可调。电路采用0.35μm标准CMOS工艺进行流片。测试结果显示,电路中心频率调节精度为0.8 kHz。该电路结构简单、容易集成,可广泛应用于红外遥控接收系统。     

一种基于Gm-C的高Q值模拟中频带通滤波器设计与实现

设计并实现了一种基于Gm-C二次节(Biquad)结构的6阶切比雪夫Ⅰ型模拟中频带通滤波器,中心频率为46MHz,带宽为2.046MHz.其中Biquad结构中加入了负阻抗单元,增加输出阻抗,实现滤波器的高Q值(品质因数).跨导放大器(Operational transconductance amplifier,OTA)单元使用源极负反馈技术,优化了OTA的线性性能.整个滤波器电路采用0.35μm CMOS工艺实现.经过仿真验证,滤波器的通带纹波是2.704dB,1.5倍带宽处衰减大于21dB.在3.3V电源电压情况下,滤波器的总电流消耗为8.87mA.     

A Linear CMOS OTA and Its Application to a 3.3V 20MHz High-Q gm-C Bandpass Filter

A design of a linear and fully-balanced operational transconductance amplifier (OTA) with improved high DC gain and wide bandwidth is presented.Derivative from a single common-source field effect transistor (FET) cascade and its DC I-V characteristics,the third-order coefficient g3 has been well compensated with a parallel FET operated in the triode region,which has even-odd symmetries between the boundary of the saturation and triode region.Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters.A negative resistance load (NRL) technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes.Additionally,derivations from the ideal -90. phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest.HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply.As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0.18μm CMOS process with two kinds of gate-oxide layers,which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.     

3V 10b 70 MHz CMOS D/A converter for video applications

This work describes a 10 b 70 MHz CMOS digital-to-analogue converter (DAC) for video applications. The proposed DAC is composed of a unit decoded matrix for 7 MSBs and a binary weighted array for 3 LSBs, considering linearity, power consumption, routing area and glitch energy. A new switching scheme for the unit decoded matrix is developed to further improve the linearity. Cascode current sources and differential switches with a new deglitching circuit improve the dynamic performance     

A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.Kâre T. Christensen received the M.Sc. and Ph.D. degrees in electrical engineering from the Technical University of Denmark in 1997 and 2002, respectively.In 1995-96 he was a visiting scholar working on switched current memory cells at the Spanish National Microelectronics Centre in Seville. In 1997 he worked on an asynchronous embedded MIPS16/MIPS32 microprocessor core for LSI Logic. In 1999-2000 he was a visiting researcher at Stanford University. During his stay he worked on fully integrated RF front-end filters in CMOS.From 1998 to 2002 he worked for Nokia Mobile Phones conducting research in the design of RF ICs for multi-band GSM terminals. He currently works for the Danish hearing aid manufacturer Oticon A/S designing micro-power RF circuits and systems in CMOS.He has lectured on several occasions at the Technical University of Denmark and other universities. He has authored or co-authored nine papers and holds three U.S. patents.Thomas H. Lee received the S.B., S.M. and Sc.D. degrees in electrical engineering, all from the Massachusetts Institute of Technology in 1983, 1985, and 1990, respectively.He joined Analog Devices in 1990 where he was primarily engaged in the design of high-speed clock recovery devices. In 1992, he joined Rambus Inc. in Mountain View, CA where he developed high-speed analog circuitry for 500 megabyte/s CMOS DRAMs.He has also contributed to the development of PLLs in the StrongARM, Alpha and AMD K6/K7/K8 microprocessors. Since 1994, he has been a Professor of Electrical Engineering at Stanford University where his research focus has been on gigahertz-speed wireline and wireless integrated circuits built in conventional silicon technologies, particularly CMOS.He has twice received the Best Paper award at the International Solid-State Circuits Conference, co-authored a Best Student Paper at ISSCC, was awarded the Best Paper prize at CICC, and is a Packard Foundation Fellowship recipient.He is an IEEE Distinguished Lecturer of both the Solid-State Circuits and Microwave Societies. He holds 35 U.S. patents and authored The Design of CMOS Radio-Frequency Integrated Circuits (now in its second edition), and Planar Microwave Engineering, both with Cambridge University Press. He is a co-author of four additional books on RF circuit design, and also cofounded Matrix Semiconductor.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from the Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, IL devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ÿrstedïDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.     

A CMOS A/D Converter with Piecewise Linear Characteristic and Its Application to Sensor Linearization

A novel 8-bit CMOS A/D converter with piecewise linear characteristic is designed, implemented and tested. It can be regarded as a two-stage flash A/D converter. The resulting architecture can be applied to the linearization of nonlinear characteristics of a wide variety of sensors, just adapting the break points of the piecewise linear characteristic to get the best-fit approach to the inverse of the sensor characteristic under consideration. A very compact implementation is obtained, since two-stage A/D conversion and linearization are both performed simultaneously by the same circuit and because both A/D conversion stages share most of the required hardware. As a particular example, a sinusoidal nonlinearity, typical of several types of solid-state sensors, is compensated in this paper. Measurement results for a 2 m CMOS prototype demonstrate the validity of the proposed approach.     

一种用于900MHz射频识别(RFID)读写器芯片的1.8VCMOS直接变频接收机

设计了针对解决900MHz RFID读写器收发机芯片中本地载波干扰问题而优化的直接变频接收机,并在0.18μm 1P6M混合信号CMOS工艺上实现验证.设计中使用了一种串联反馈结构的基带放大器以达到同时实现无源混频器输出缓冲,直流消除以及信号放大的功能.实际测量显示,该接收机的输入1dB压缩点为-4dBm,当中频信号解调信噪比要求为10dB时,可达到的灵敏度为-70dBm.该接收机与整个收发机集成在同一块芯片中,使用1.8V电源电压,工作时静态电流为90mA.     

一种用于900MHz射频识别（RFID）读写器芯片的1.8V CMOS直接变频接收机

设计了针对解决900MHz RFID读写器收发机芯片中本地载波干扰问题而优化的直接变频接收机,并在0.18μm 1P6M 混合信号CMOS工艺上实现验证. 设计中使用了一种串联反馈结构的基带放大器以达到同时实现无源混频器输出缓冲,直流消除以及信号放大的功能. 实际测量显示,该接收机的输入1dB压缩点为-4dBm,当中频信号解调信噪比要求为10dB时,可达到的灵敏度为-70dBm. 该接收机与整个收发机集成在同一块芯片中,使用1.8V电源电压,工作时静态电流为90mA.     

A 200 MHz 4.8 mW 3 V Fully Differential CMOS Sample-and-Hold Circuit with Low Hold Pedestal

Wide frequency bandwidth has been internationally allocated for unlicensed operation around the oxygen absorption frequency at 60 GHz. A power amplifier and a low noise amplifier are presented as building blocks for a T/R-unit at this frequency. The fabrication technology was a commercially available 0.15 m gallium arsenide (GaAs) process featuring pseudomorphic high electron mobility transistors (PHEMT). Using on-wafer tests, we measured a gain of 13.4 dB and a +17 dBm output compression point for the power amplifier at 60 GHz centre frequency when the MMIC was biased to 3 volts V_dd. At the same frequency, the low noise amplifier exhibited 24 dB of gain with a 3.5 dB noise figure. The AM/AM and AM/PM characteristics of the power amplifier chip were obtained from the large-signal S-parameter measurement data. Furthermore, the power amplifier was assembled in a split block package, which had a WR-15 waveguide interface in input and output. The measured results show a 12.5 dB small-signal gain and better than 8 dB return losses in input and output for the packaged power amplifier.Mikko Kärkkäinen received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2000, and is currently working toward the Ph.D. degree at the Electronic Circuit Design Laboratory, Helsinki University of Technology. He is interested in millimetre wave circuit design.Mikko Varonen received the M.Sc. degree in electrical engineering from the Helsinki University of Technology, Espoo, Finland, in 2002. He is currently working toward the Ph.D. degree in electrical engineering at the Electronic Circuit Design Laboratory, Helsinki University of Technology. His research interests involve millimetre-wave integrated circuits.Pekka Kangaslahti received the M.Sc. and Ph.D. degrees in electrical engineering from the Helsinki University of Technology, Finland, in 1992 and 1999, respectively. Since 1999 he has been a visiting scientist at the NASA Jet Propulsion Laboratory, Pasadena, USA. His research interests include nonlinear microwave and millimetre wave monolithic circuits, especially for signal generation in telecommunication and radar applications.Kari A. I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987.From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Center of Finland. From 1984 to 1987 he was a research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Center (1990–1993). He was on leave of absence the academic year 1992–93, acting as R&D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of Electrical Engineering and Telecommunications, Helsinki University of Technology. He became the Head of Electronic Circuit Design Laboratory year 1998. From 1997 to 1999 he was an associate editor of IEEE Transactions on Circuits and Systems I. He has been a guest editor for IEEE Journal of Solid-State Circuits and the Technical Program Committee Chairman for European Solid-State Circuits Conference year 2000. He has been awarded the Beatrice Winner Award in ISSCC02 Conference year 2002.     

A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 Voperation

This paper describes a phase-locked loop (PLL) based frequency synthesizer. The voltage-controlled oscillator (VCO) utilizing a ring of single-ended current-steering amplifiers (CSA) provides low noise, wide operating frequencies, and operation over a wide range of power supply voltage. A programmable charge pump circuit automatically configures the loop gain and optimizes it over the whole frequency range. The measured PLL frequency ranges are 0.3-165 MHz and 0.3-100 MHz at 5 V and 3 V supplies, respectively (the VCO frequency is twice PLL output). The peak-to-peak jitter is 81 ps (13 ps rms) at 100 MHz. The chip is fabricated with a standard 0.8-μm n-well CMOS process