CMOS photodiode with enhanced responsivity for the UV/blue spectralrange

A new photodiode for the UV/blue spectral range, which can be integrated monolithically with CMOS circuits, is presented. Such optoelectronic integrated circuits (OEICs) with a high sensitivity in the UV/blue spectral range are needed in near-future optical storage systems like digital versatile disk (DVD) or digital video recording (DVR). At 400 nm, our so-called finger photodiode achieves a responsivity of 0.23 A/W corresponding to a quantum efficiency η of 70% [with an antireflection coating (ARC)] and rise and fall times of 1.0 ns and 1.1 ns, respectively. The finger photodiode can be used in the red spectral range, too. At 638 nm, the responsivity is 0.49 A/W (η=95%) and rise and fall times of less than 2.3 ns are achieved. For the integration of the finger photodiode in an industrial 1 μm twin-well CMOS process, only one additional mask is needed in order to block out the threshold voltage implantation in the photo-active region     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

CMOS图像传感器及其研究

介绍了CMOS图像传感器的工作原理,比较了CCD图像传感器与CMOS图像传感器的优缺点,指出了CMOS图像传感器的技术问题和解决途径,综述了CMOS图像传感器的现状和发展趋势.     

CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 μm double-poly, double-metal foundry CMOS process and is realized as a 128×128 array of 40 μm×40 μm pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications     

Smart CMOS image sensor arrays

In this paper, we present several smart image sensor arrays intended for various applications. We discuss the realization of image sensors in CMOS technology and show some examples of one-dimensional (1-D) and two-dimensional (2-D) smart image arrays     

CMOS图像传感器的辐射实验

为了考察商用CMOS图像传感器应用于空间的可行性,对进行了空间辐射环境模拟实验研究.实验采用60Co-γ辐射源模拟空间辐射环境,辐射最大剂量为5× 104 rad(Si),辐射速率为1 Gy/s.在辐照时,根据实验需要在CMOS两端加偏置电压或不加偏置电压,并采用在线和离线测量相结合的方法.实验结果表明:辐射初期各项性...     

CMOS图像传感器新技术——C^3D

C3D(CMOS Color Captive Device)是新一代半导体成像技术,它不仅提高了像素设计技术,也改进了生产工艺.采用这种技术生产的0.25 μ mCMOS图像传感器能够在不牺牲性能的前提下增加晶体管的数量和占空因数(Fill Factor).除了增加像素设计的选择方案之外,还可实现更为复杂的功能和更低的功耗,并且在速度方面也很有优势.     

CMOS图象传感器的原理及应用

CMOS图象传感器是多功能、高性能的摄象器件。本文详细介绍了其工作原理及其在微型摄象机、数码相机、医学等方面的应用     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers

A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25-/spl mu/m CMOS technology with pinned photodiodes gave an rms random noise of 263 /spl mu/V and an rms fixed pattern noise of 50 /spl mu/V.     

A CMOS image sensor with a double-junction active pixel

A CMOS image sensor that employs a vertically integrated double-junction photodiode structure is presented. This allows color imaging with only two filters. The sensor uses a 184*154 (near-QCIF) 6-transistor pixel array at a 9.6-/spl mu/m pitch implemented in 0.35-/spl mu/m technology. Results of the device characterization are presented. The imaging performance of an integrated two-filter color sensor is also projected, using measurements and software processing of subsampled images from the monochrome sensor with two color filters.     

A logarithmic response CMOS image sensor with on-chip calibration

CMOS image sensors with logarithmic response are attractive devices for applications where a high dynamic range is required. Their strong point is the high dynamic range. Their weak point is the sensitivity to pixel parameter variations introduced during fabrication. This gives rise to a considerable fixed pattern noise (FPN) that deteriorates the image quality unless pixel calibration is used. In the present work a technique to remove the FPN by employing on-chip calibration is introduced, where the effect of threshold voltage variations in pixels is cancelled. An image sensor based on an active pixel structure with five transistors has been designed, fabricated, and tested. The sensor consists of 525×525 pixels measuring 7.5 μm×10 μm, and is fabricated in a 0.5-μm CMOS process. The measured dynamic range is 120 dB while the FPN is 2.5% of the output signal range     

Space-variant nonorthogonal structure CMOS image sensor design

A CMOS log-polar image sensor has been designed and fabricated. As a result, a systematic approach has been proposed to design space-variant sensors and layouts. The pixels in this sensor are distributed in a polar fashion; the image plane consists of concentric rings containing the elementary sensing cells. Such a structure, where polygons use any space orientation, does not match very well with current design tools and CMOS fabrication processes. An approach to design nonorthogonal repetitive structures using standard fabrication processes and computer-aided design (CAD) tools is presented. The result of this work is an image sensor, with log-polar structure, suitable for image processing since the log-polar mapping has interesting mathematical and image data reduction properties     

CMOS图像传感器简议

数码相机和可拍照式便携设备的兴起，使得CMOS图像传感器这个名词进入大众的视野，而这种产品也成为了半导体产品中增长最快的一种。其实，在几年前，CMOS传感器还没有今天这样耀眼的地位，那时的它还只能仰望强大的对手CCD传感器。但是，仅仅是几年的功夫，它就可以同CCD分庭抗礼了。     

A 128-pixel CMOS image sensor with integrated analog nonvolatilememory

A 128-pixel complementary metal-oxide-semiconductor (CMOS) image sensor array with analog nonvolatile storage for each pixel has been realized in a 1.5-μm single-poly standard CMOS/EEPROM technology and successfully tested. The integrated nonvolatile memory allows an offset correction for each sensor element, cancellation of the fixed pattern noise, and compensation of the background illumination. The sensor array can also learn a presented pattern and store it in its analog nonvolatile memory just by “seeing”. The stored pattern can be read out directly or, in combination with the optical input, it can be used for pattern recognition or motion detection. The required programming circuitry for the analog memory has been integrated on the same chip     

CMOS active pixel image sensor with simple floating gate pixels

A new pixel structure using a simple floating gate (SFG) has been proposed. The pixel consists of a coupling capacitor, a photogate, a barrier gate and a MOS transistor. It features complete reset that results in no kTC noise and no image lag, high blooming overload protection, nondestructive readout (NDRO), and CMOS compatibility. Its basic operation has been confirmed with a 32(H)×27(V) pixel area array. Since the pixel structure is relatively simple, small pixel size is feasible     

A time-to-first spike CMOS image sensor with coarse temporal sampling

Conventional voltage-based CMOS image sensors inherently have a dynamic range of about 60 dB. To extend the dynamic range, a two-degree of freedom time-based CMOS image sensor is proposed. Instead of reading analog voltages off chip, a time representation is used to record when the photodetector voltage passes a timing-varying threshold. The time measurements are combined with the reference voltage waveform to reconstruct the image. Experimental results on a prototype 32 × 32 pixel array CMOS image sensor verify that the two-degree of freedom sampling technique is feasible for ultra-wide dynamic range imaging. A measured 115 dB dynamic range at 30 fps is obtained. Qiang Luo received the B.S. (with honor) and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 1995 and 1998, respectively, and the Ph.D. degree in electrical engineering from University of Florida, Gainesville, FL, in 2002. In 2001, he was with Texas Instruments Inc., Dallas, TX, where he was an intern engineer working on ultra-wide dynamic range CMOS image sensors. From 2002 to 2004, he was with National Semiconductor Corporation, Santa Clara, CA, where he was a staff circuit design engineer and worked on the design of high performance CMOS image sensors. He is currently with the Marvell Semiconductor Inc, Sunnyvale, CA, where he is working on the development of advanced DVD servo IC. His research interests include high-speed mixed-signal IC design, CMOS image sensors, DVD servo IC and device physics. Dr. John G. Harris received his BS and MS degrees in Electrical Engineering from MIT in 1983 and 1986. He earned his PhD from Caltech in the interdisciplinary Computation and Neural Systems program in 1991. After a two-year postdoc at the MIT AI lab, Dr Harris joined the Electrical and Computer Engineering Department at the University of Florida (UF). He is currently an associate professor and leads the Hybrid Signal Processing Group in researching biologically-inspired circuits, architectures and algorithms for signal processing. Dr. Harris has published over 100 research papers and patents in this area. He co-directs the Computational NeuroEngineering Lab and has a joint appointment in the Biomedical Engineering Department at UF. Zhiliang J. Chen received Ph.D. degree in electrical engineering from University of Florida in 1994. From 1994 to 2004, he was with Texas Instruments where he worked as Senior Member of Technical Staff and Design Branch Manager. In 2002 he was expatriated to COMMIT, a Texas Instruments JV company in China, as director of RF & Analog Base Band department. In 2004, he left Texas Instrument and found On-Bright (Shanghai) Corporation where he serves as president of the company. Dr. Chen currently held 22 US patents and has published morn than 10 journal papers. He was a recipient of the Best Paper Award from the 1997 ESD/EOS symposium.     

CMOS图像传感器的图像采集系统的研究与实现

研究一种基于USB2D的CMOS图像传感器的图像采集系统的实现方案.以xilinx公司的FPGA芯片为核心控制芯片,Cypress公司的CY7C68013为USBZ0接口芯片.主要介绍了CMOS图像传感器外围电路设计、FPGA芯片与CMOS图像传感器接口电路设计、FPGA芯片与USB模块的接口电路设计.所设计的采集系统功耗低、成本低、可扩展性强.     

Wide dynamic range CMOS image sensor with pixel level ADC

A new enhanced dynamic range (DR) and signal-to-noise ratio (SNR) CMOS imaging system with a pixel level analogue-to-digital converter (ADC) is presented. The proposed reset technique and time-to-digital converter increases DR and peak SNR simultaneously. The circuit reuse concept is also proposed to increase the fill factor.     

Color mixing improvement of CMOS image sensor with air-gap-guard ring in deep-submicrometer CMOS technology

In this letter, color mixings of a CMOS image sensor with air-gap-guard-ring (AGGR) and conventional structures were investigated in 0.18-/spl mu/m CMOS image sensor technology. As the light incident angle is increased from 0/spl deg/ to 15/spl deg/, conventional pixel shows serious color mixing. For example, the maximum photo responses of blue, green1, green2, and red pixels are shifted from 490 to 520 nm, 530 to 500 nm, 530 to 600 nm, and 600 to 580 nm, respectively. However, pixels with AGGR not only keep correct spectral response without peak shift but also achieve 5%-50% crosstalk reduction, thus preventing the sensor from color mixing efficiently.