Improving gate-oxide reliability by TiN capping layer on NiSi FUSI metal gate

The impact of TiN capping layer on gate oxide reliability of NiSi fully silicided metal gate was investigated. It was found that the TiN capping layer significantly improved V/sub th/ stability and oxide reliability during negative bias temperature stress. Better life-time performance was also extrapolated for the samples with TiN capping layer.     

Dopant-free FUSI Pt/sub x/Si metal gate for high work function and reduced Fermi-level pinning

High work function (4.9 eV) on high-/spl kappa/ gate dielectric, which is suitable for bulk p-MOSFET, has been achieved using fully silicided (FUSI) Pt/sub x/Si gate without boron predoping of polysilicon. High concentration of Pt in FUSI Pt/sub x/Si using Ti capping layer on Pt in the FUSI process is a key to achieving high work function and reduced Fermi-level pinning on high-/spl kappa/ dielectric. By combining with substituted Al (SA) gate for nMOSFET, a wide range of work function difference (0.65 eV) between n and pMOSFETs is demonstrated, without any adverse effects of polysilicon predoping.     

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

A complete determination of the effective work functions (WF) of NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si on HfSiON and on SiO/sub 2/ is presented. Conditions for formation of fully silicided (FUSI) gates for NiSi/sub 2/, NiSi, Ni/sub 3/Si/sub 2/, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si crystalline phases were identified. A double thickness series (HfSiON/SiO/sub 2/) was used to extract WF on HfSiON accounting for charge effects. A strong effect on WF of Ni content is observed for HfSiON, with higher WF for the Ni-rich silicides suggesting unpinning of the Fermi level. A mild dependence is observed for SiO/sub 2/. While all Ni-rich silicides have adequate WF for pMOS applications, Ni/sub 2/Si is most attractive due to its low formation temperature, lower volume expansion and ease of integration. Similar threshold voltages (-0.3 V) were obtained on Ni/sub 2/Si and Ni/sub 31/Si/sub 12/ FUSI HfSiON pMOSFETS.     

Study of nickel silicide contact on Si/Si/sub 1-x/Ge/sub x/

The properties of nickel silicide formed by depositing nickel on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer are compared with that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer formed by depositing Ni directly on p/sup +/-Si/sub 1-x/Ge/sub x/ layer without silicon consuming layer. After thermal annealing, nickel silicide on Si/p/sup +/-Si/sub 1-x/Ge/sub x/ layer shows lower sheet resistance and specific contact resistivity than that of nickel germanosilicide on p/sup +/-Si/sub 1-x/Ge/sub x/ layer. In addition, small junction leakage current is also observed for nickel silicide on a Si/p/sup +/-Si/sub 1-x/Ge/sub x//n-Si diode. In summary, with a Si consuming layer on top of the Si/sub 1-x/Ge/sub x/, the nickel silicide contact formed demonstrated improved electrical and materials characteristics as compared with the nickel germanosilicide contact which was formed directly on the Si/sub 1-x/Ge/sub x/ layer.     

On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.     

High work function Ir/sub x/Si gates on HfAlON p-MOSFETs

We have fabricated the fully silicided Ir/sub x/Si-gated p-MOSFETs on HfAlON gate dielectric with 1.7-nm equivalent oxide thickness. After 950/spl deg/C rapid thermal annealing, the fully Ir/sub x/Si/HfAlON device has high effective work function of 4.9 eV, high peak hole mobility of 80 cm/sup 2//V/spl middot/s, and the advantage of being process compatible to the current VLSI fabrication line.     

Modeling of tunneling currents through HfO/sub 2/ and (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks

We present a physical modeling of tunneling currents through ultrathin high-/spl kappa/ gate stacks, which includes an ultrathin interface layer, both electron and hole quantization in the substrate and gate electrode, and energy band offsets between high-/spl kappa/ dielectrics and Si determined from high-resolution XPS. Excellent agreements between simulated and experimentally measured tunneling currents have been obtained for chemical vapor deposited and physical vapor deposited HfO/sub 2/ with and without NH/sub 3/-based interface layers, and ALD Al/sub 2/O/sub 3/ gate stacks with different EOT and bias polarities. This model is applied to more thermally stable (HfO/sub 2/)/sub x/(Al/sub 2/O/sub 3/)/sub 1-x/ gate stacks in order to project their scalability for future CMOS applications.     

Effect on ion implanted germanium profile on the characteristics of Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors

An optimum profile for Ge ion implantation in SiGe/Si heterojunction bipolar transistors is determined by using a two-dimensional simulator code for advanced semiconductor devices. The simulation code is based on a two-dimensional drift-diffusion model for heterostructure degenerate semiconductors with nonparabolicity included in the energy band structure. The model allows accurate simulations of carrier transport in short base devices. The simulation results indicate that for high current gain the Ge profile maximum must be close to the base-collector junction, and that the unavoidable tail of the implanted germanium in the collector region does not deteriorate the gain.<>     

A novel strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFET with an ALD TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.     

Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO/sub 2/ and HfO/sub 2/

In this letter, we investigate a method to adjust the gate work function of an MOS structure by stacking two metals with different work functions. This method can provide work function tunability of approximately 1 eV as the bottom metal layer thickness is increased from 0 to about 10 nm. This behavior is demonstrated with different metal combinations on both SiO/sub 2/ and HfO/sub 2/ gate dielectrics. We use capacitance-voltage (C-V) characteristics to investigate the effect of different annealing conditions and different metal/metal bilayer couples on the work function. By comparing the as-deposited and annealed films, and by comparing with metals that are relatively inert with each other, we deduce that the work function tuning behavior likely involves metal/metal interdiffusion.     

Precise Millimeter-Wave Measurements of Complex Refractive Index, Complex Dielectric Permittivity and Loss Tangent of GaAs, Si, SiO/sub 2/, A1/sub 2/O/sub 3/, BeO, Macor, and Glass

Highly accurate continuous spectra of the complex refractive index and complex dielectric permittivity are given in the millimeter range for a variety of potentially useful materials. The absorption coefficient is found to increase monotonically with increasing frequencies. Small amounts of glassy inclusions or water were found to increase losses at all frequencies, but impurities and radiation damage (except in semiconductors) have not yet proved to be detrimental to performance. Materials have been found for which the millimeter-wave losses can be tolerated when used as dielectric waveguide, high-power windows, and other applications. Nominal consideration must be given, however, to the conditions of preparation and the nature of contaminants, The measurements were made in a modular, polarizing, dispersive Fourier-transform spectrometer.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

Annealing effect on the metal gate effective work function modulation for the Al/TiN/SiO2/p-Si structure

In this work, the thermal annealing effect on the metal gate effective work function (EWF) modulation for the Al/TiN/SiO₂/p-Si(1 0 0) structure was investigated. Compared with the sample of TiN/SiO₂/p-Si(1 0 0) structure, for the sample additionally capped with Al the flat band voltage has a very obvious shift as large as 0.54 V to the negative direction after forming gas annealing. It is also revealed that the thermal budget can effectively influence both the EWF of the gate electrode and the thickness of the gate dielectric layer when a post annealing at 600 °C with different soak times was applied to the samples with Al cap. Material characterization indicates that the diffusion of Al and the formation of Al oxide during annealing should be responsible for all the phenomena. The interface trap density Dit calculated from the high-frequency C-V and the laser-assisted high-frequency C-V curves show that the introduction of Al does not cause reliability problem in the Al/TiN/SiO₂/p-Si structure.     

The microwave power performance comparisons of Al/sub x/Ga/sub 1-x/As/In/sub 0.15/Ga/sub 0.85/As (x=0.3, 0.5, 0.7, 1.0) doped-channel HFETs

The properties of doped-channel field-effect transistors (DCFET) have been thoroughly investigated on Al/sub x/Ga/sub 1-x/As/InGaAs (x= 0.3, 0.5, 0.7, 1) heterostructures with various Al mole fractions. In this study, we observed that by introducing a 200-/spl Aring/-thick Al/sub 0.5/Ga/sub 0.5/As (x=0.5) Schottky layer can enhance the device power performance, as compared with the conventional x=0.3 AlGaAs composition system. However, a degradation of the device power performance was observed for further increasing the Al mole fractions owing to their high sheet resistance and surface states. Therefore, Al/sub 0.5/Ga/sub 0.5/As Schottky layer design provides a good opportunity to develop a high power device for power amplifier applications.     

Epitaxial growth of metallic ErP, ErSb and lattice-matched ErP/sub x/Sb/sub (1-x)/ layers on

ErP and ErSb compounds have been demonstrated to have metallic behaviour ( rho /sub ErP/=150 mu Omega cm; rho /sub ErSb/=60 mu Omega cm). The authors show that they can be epitaxially grown on InP and GaAs in an MBE system and that many matched systems (metallic layer)/(III-V semiconductor) can be built using ternary compounds of rare-earth and V elements.<>     

Investigation of the impact of Al mole-fraction on the consequences of RF stress on Al/sub x/Ga/sub 1-x/N/GaN MODFETs

Variations of the low-frequency noise (LFN), power, and dc characteristics of a variety of SiN/sub x/ passivated AlGaN/GaN MODFETs with different values of Al mole-fraction, gate length, and gate drain spacing upon RF stress are investigated. It is experimentally evidenced that the variation of Al mole-fraction (x) of the barrier Al/sub x/Ga/sub 1-x/N layer from 0.2 to 0.4, has no considerable impact on the drain and gate low-frequency noise current characteristics. The most noticeable variation on the device characteristics upon long-term RF stressing has been on the pinch-off voltage. Although no material degradation by increasing the Al mole-fraction has been evidenced through the low-frequency noise data, it is observed that the variation of pinch-off voltage upon RF stressing becomes more important as the Al mole-fraction increases.     

Effect of Mg doping on the superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta//

Superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// (Cu/sub 1-x/Tl/sub x/Mg/sub y/-1234) material have been studied in the composition range y=0,1.5,2.25. The zero resistivity critical temperature [T/sub c/(R=0)] was found to increase with the increased concentration of Mg in the unit cell; for y=1.5 [T/sub c/(R=0)]=131 K was achieved which is hitherto highest in Cu/sub 1-x/Tl/sub x/-based superconductors. The X-ray diffraction analyses have shown the formation of a predominant single phase of Cu/sub 0.5/Tl/sub 0.5/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// superconductor with an inclusion of impurity phase. It is observed from the convex shape of the resistivity versus temperature measurements that our as-prepared material was in the region of carrier over-doping, and the number of carriers was optimized by postannealing experiments in air at 400/spl deg/C, 500/spl deg/C, and 600/spl deg/C. The T/sub c/(R=0) was found to increase with postannealing and the best postannealing temperature was found to be 600/spl deg/C. The mechanism of increased T/sub c/(R=0) is understood by carrying out infrared absorption measurements. It was observed through softening of Cu(2)-O/sub A/-Tl apical oxygen mode that improved interplane coupling was a possible source of enhancement of T/sub c/(R=0) to 131 K.     

Top-TiN生长条件及TaN厚度对MOSCAP栅叠层有效功函数的影响

我们引入TaN/TiAl/top-TiN三层结构,通过变化TaN的厚度及top-TiN的生长条件来调节TiN-based金属栅叠层的有效功函数。实验结果显示：较薄的TaN和PVD-process生长的top-TiN组合可以得到较小的有效功函数(EWF),而较厚的TaN和ALD-process生长的top-TiN组合可以得到较大的有效功函数(EWF),文中EWF有从4.25eV to 4.56eV的变化。同时文中也给出了TaN厚度及top-TiN的生长条件调节有效功函数(EWF)的物理解释。与PVD-process在室温条件下生长TiN相比,ALD-process TiN是在400 ℃条件下生长的,400 ℃ ALD-process TiN 可以为整个工艺过程提供更多的热预算,从而促进更多的Al原子扩散进入top-TiN,导致扩散进入到bottom-TiN的Al原子数量减少。另外,厚的TaN也会阻止Al原子进入bottom-TiN。这些因素都减少了bottom-TiN中Al原子的数量,减弱了Al原子对有效功函数的调节作用,从而引起EWF的增加。