Algorithmic Exploration and Implementation of a MIMO-OFDM Equalizer

In this paper we explore algorithms and architectures for the implementation of a MIMO OFDM Equalizer for high speed wireless communications. The algorithmic exploration is based on matrix computations and factorizations. A scalable computational methodology and architecture is proposed for the implementation of a 4×4 MIMO OFDM. A 2×3 Equalizer supporting Maximum Ratio Combining and Zero Forcing equalization for 20/40 MHz 64-QAM OFDM modulation has been implemented in 150 nm technology. The Equalizer area is 133k gates and the maximum throughput achieved is 480Mbits/s. The system described in this paper is compliant with the latest IEEE standard for MIMO wireless communications (802.11n)     

A new teletext character set with enhanced legibility

Teletext is difficult to read, partly because of the letter fonts employed. Present fonts are contained in a matrix of 6 (horizontal) × 10 (vertical) elements. Research on matrix characters of optimum legibility started in 1969 at the Institute for Perception Research. Criteria resulting from this research have now been used to design alphanumeric characters in a matrix of 12 × 10 elements for use in Teletext. Several versions of each character were designed and their legibility tested in recognition experiments. The legibility of the best new version for each letter was compared with and shown generally to be greater than that of the presently used version.     

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling

Sub-threshold designs have become a popular option in many energy constrained applications. However, a major bottleneck for these designs is the challenge in attaining timing closure. Most of the paths in sub-threshold designs can become critical paths due to the purely random process variation on threshold voltage, which exponentially impacts the gate delay. In order to address timing violations caused by process variation, post-silicon tuning is widely used through body biasing technology, which incurs heavy power and area overhead. Therefore, it is imperative to select only a small group of the gates with body biasing for post-silicon-tuning. In this paper, we first formulate this problem as a linear semi-infinite programming (LSIP). Then an efficient algorithm based on the novel concept of Incremental Hypercubic Sampling (IHCS), specially tailored to the problem structure, is proposed along with the convergence analysis. Compared with the state-of-the-art approach based on adaptive filtering, experimental results on industrial designs using 65 nm sub-threshold library demonstrate that our proposed IHCS approach can improve the pass rate by up to 7.3× with a speed up to 4.1×, using the same number of body biasing gates with about the same power consumption.     

A high luminance high-resolution cathode-ray tube for special purposes

For those applications where light sources of high radiance or displays of high resolution are necessary, miniature cathode-ray tubes have been developed with monocrystalline luminescent screens. These newly developed screens consist of cerium-doped yttrium-aluminum garnet (YAG), epitaxially grown on commercially available YAG substrates; they have an excellent heat conductivity and are optically clear. The construction of the tube and its performance in two modes of operation are described. When the tube is operated with a continuous undeflected beam, the luminance of the spot is limited by thermal quenching of the phosphor material. Under these circumstances, the maximum luminance of 1.9 × 10⁸cd/m²(0.55 × 10⁸FTL or 4 × 10⁵W/m²sr) is reached at a power of 70 mW in a 3.5-µA 20-kV beam, focussed to a spot of 9 µm diameter. Equipped with appropriate deflection coils and scanned with an interlaced field of 575 active lines and 25-Hz repetition frequency, the tube can handle up to 20 W of beam power in a 12 × 16 mm²image area. In this mode, the luminance is limited by the design of the electron gun and the desired resolution. At 20 kV and 100 µA (i.e., at 7500 cd/m²) the tube has a half-intensity linewidth of 60 µm, which is equivalent to 500-TV limiting response lines in the same 12 × 16 mm²area.     

An 8?×?8 20?Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking

In this paper, we propose a reconfigurable load balanced symmetric TDM switch fabric. We fold this two-stage switch to reduce 50% hardware complexity, and then implement a 3.65?mm?×?3.57?mm prototype switch fabric IC, including a digital 8?×?8 switch core, eight 16B20B CODECs, eight SERDES ports, eight CML I/O interfaces and a PLL, in 0.18???m CMOS technology. The digital 8?×?8 switch core has reconfigurable connection patterns for the ease of scaling up to an N×N switch (N is power of 4). We propose the 16B20B CODEC scheme to reduce the switch core clock rate by half. In the SERDES, we employ the half-rate scheme and then use static CMOS gates for the low power consumption. We develop a low power, area-efficient and wide-band CML I/O interface with our patented PMOS active load inductive-peaking scheme for high-speed data transmission. With the 16B20B CODEC, the half-rate, and the PMOS active load schemes, almost 50% of the power is saved as compared with the design of the 8B10B CODEC, the full-rate and on-chip inductors CML schemes. Our measurement shows that an 8?×?8 switch fabric IC can achieve 20?Gbps switching rate and consumes only about 690?mW power. A terabit switch fabric can then be constructed by cascading the designed switch ICs.     

A magnetic-particles display

A new type of flat-panel ambient-illuminated display is described. Images in this display are formed by magnetically controlling the orientations of small spherical multicolored magnetic particles. A demonstration model is shown and the possibility for application to television is studied. It is estimated that for a 9 × 12-cm black-and-white screen with built-in magnetic memory and 500 × 500 sequential matrix addressing the display panel can be driven at TV rates with an average current of 0.27 A and dissipation of 0.26 W. Contrast ratios up to 40:1 seem achievable with continuously variable grays. The display also features a nonvolatile memory which can be very desirable for some applications. Methods for fabricating this display are also discussed.     

Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50 nm double gate devices

Double gate (DG) FETs have emerged as the most promising technology for sub-50 nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, viz., doped body symmetric device (SymDG) with polysilicon gates, intrinsic body symmetric device with metal gates (MGDG) and intrinsic body asymmetric device (AsymDG) with different front and back gate materials. It is observed that, use of (near-mid-gap) metal gate and intrinsic body can result in 3–4× reduction in gate-to-channel leakage compared to the SymDG structure.     

A technique to mitigate impact of process,voltage and temperature variations on design metrics of SRAM Cell

This paper presents a technique for designing a variability aware SRAM cell. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that the access pass gates are replaced with full transmission gates. The paper studies the impact of V_t (threshold voltage) variation on most of the design metrics of SRAM cell. The proposed design achieves 1.4× narrower spread in I_READ at the expense 1.2× lower I_READ at nominal V_DD. It offers 1.3× improvements in T_RA (read access time) distribution at the expense of 1.2× penalty in read delay. The proposed bitcell offers 1.1× tighter spread in T_WA (write access time) incurring 1.3× longer write delay. It shows 180 mV of SNM (static noise margin) and is equally stable in hold mode. It offers 1.3× higher RSNM (100 mV) compared to 6T (75 mV). It exhibits improved SINM (static current noise margin) distribution at the expense of 1.6× lower WTI (write trip current). It offers 1.05× narrower spread in standby power. Thus, comparative analysis based on Monte Carlo simulation exhibits that the proposed design is capable of mitigating impact of V_t variation to a large extent.     

Uniformity of the Electron Number Density in a Mercury Discharge Tube†

The possible uses of threshold logic gates in sequential design problems is investigated, and circuit configurations disclosed. Whilst it is shown that threshold gates can be used to perform all the functions now carried out with Boolean-typo gates, it is concluded that only in the realm of ring and chain counters does threshold realization shove any potential economic advantage.     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.     

A WNxgate self-aligned GaAs p-channel MESFET for complementary logic

The Schottky barrier of reactively sputtered WNxto p-type GaAs has been investigated. Postdeposition heat treatments above 500°C led to a reduction in the barrier height but for lamp annealing at 740°C the barrier heights are 0.68 eV. Self-aligned p-channel MESFET's were fabricated with WNxgates by a refractory metal process involving the above heat treatment. The Schottky-barrier heights were close to the expected values. K-values of FET's with 2 µm × 24 µm gates were 0.088 mA/V², consistent with previously reported results. SPICE simulation studies carried out for a variety of complementary-type logic gates, indicate that power dissipation × delay time products of less than 10 fJ may be achievable over the power range 5-50 µW/gate. Thus complementary logic may be useful for applications where low power dissipation is at a premium.     

Low-resolution expression recognition based on central oblique average CS-LBP with adaptive threshold

In order to solve the problem of low recognition rate of traditional feature extraction operators under low-resolution images, a novel algorithm of expression recognition is proposed, named central oblique average center-symmetric local binary pattern (CS-LBP) with adaptive threshold (ATCS-LBP). Firstly, the features of face images can be extracted by the proposed operator after pretreatment. Secondly, the obtained feature image is divided into blocks. Thirdly, the histogram of each block is computed independently and all histograms can be connected serially to create a final feature vector. Finally, expression classification is achieved by using support vector machine (SVM) classifier. Experimental results on Japanese female facial expression (JAFFE) database show that the proposed algorithm can achieve a recognition rate of 81.9% when the resolution is as low as 16×16, which is much better than that of the traditional feature extraction operators.     

Low cost high throughput pipelined architecture of 2-D 8 × 8 integer transforms for H.264/AVC

In this article, we present the implementation of high throughput two-dimensional (2-D) 8?×?8 forward and inverse integer DCT transform for H.264. Using matrix decomposition and matrix operation, such as the Kronecker product and direct sum, the forward and inverse integer transform can be represented using simple addition operations. The dual clocked pipelined structure of the proposed implementation uses non-floating point adders and does not require any transpose memory. Hardware synthesis shows that the maximum operating frequency of the proposed pipelined architecture is 1.31?GHz, which achieves 21.05 Gpixels/s throughput rate with the hardware cost of 42932 gates. High throughput and low hardware makes the proposed design useful for real time H.264/AVC high definition processing.     

Design tradeoffs between surface and buried-channel FET's

A study of the operation of surface- and buried-mode p-channel FET's is conducted. The buried-channel devices are fabricated using n-type polysilicon gates while the surface-channel devices employ p-type polysilicon gates. Using devices with different channel lengths (20 to 0.4 µm), threshold voltage lowering, subthreshold characteristics, transconductance, punchthrough, and body effects are compared over a wide range of background doping concentrations. In the study surface-channel devices were found to be more resistant to short-channel effects than their buried-channel counterparts independent of background doping concentration. Two-dimensional computer simulation revealed that buried-channel devices are more subject to drain-induced barrier lowering and bulk punchthrough. The body effect for the surface-channel device is lower than its counterpart at low background doping concentrations whereas the buried-channel device has a lower body effect at high background doping levels. The effective carrier mobility of buried-channel devices was found greater than that of surface devices. The net difference in the transconductance, however, is offset by the high parasitic diffusion resistance.     

Using multi-threshold threshold gates in RTD-based logic design: A case study

The basic building blocks for resonant tunneling diode (RTD) logic circuits are threshold gates (TGs) instead of the conventional Boolean gates (AND, OR, NAND, NOR) due to the fact that, when designing with RTDs, TGs can be implemented as efficiently as conventional ones, but realize more complex functions. Recently, RTD structures implementing multi-threshold threshold gates (MTTGs) have been proposed which further increase the functionality of the original TGs while maintaining their operating principle and allowing also the implementation of nanopipelining at the gate level. This paper describes the design of n-bit adders using these MTTGs. A comparison with a design based on TGs is carried out showing advantages in terms of power consumption and power delay product.     

Optimized reversible arithmetic logic units

Arithmetic Logic Unit(ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4(Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.     

Electromigration mechanisms in aluminum lines

Special test structures were used for investigating electromigration mechanisms. Large-grained Al lines of different lengths and widths were interconnected by varying TiN auxiliary layers. Test current densities lay between 4 × 10⁵ A/cm² and 6 × 10⁵ A/cm² at 200°C. Considering electromigration threshold, grain boundary electromigration was eliminated and interface electromigration appeared, affecting the conductive Al/TiN interface. Interface electromigration clearly contributes to the mass flow of Al lines, and thus can be detrimental for the reliability of metallization. The interface diffusion activation energy is comparable to the grain boundary activation energy. Contrary to a conductive interface, the technical Al surface does not contribute to mass flow. The elimination of interface effects finally brings out homogeneous bulk electromigration. The drift velocity was directly measured after a stress period of 8300 hours at 200°C. For a current density of 4 × 10⁵ A/cm² bulk drift velocity was 7 × 10^?12 cm/s, while grain boundary electromigration surpassed this value by a factor of 300. Electromigration threshold was ascertained for grain boundary as well as for interface and bulk diffusion.     

分块CS-LBP和加权PCA的低分辨率人脸识别

针对局部二值模式(LBP)特征在低分辨率的人脸图 像上识别率较低的问题,提出了一种基于分块中心对称局部二值模式(CS-LBP,center symmetric local binary pattern)和加权主成分分析(PCA)算法的低分辨率人脸识别算法。 首先利用分块CS-LBP算子提取低分辨率人脸图像的特征;然后利用加权PCA算子对特 征进行降维, 从而得到更强的分类特征;最后利用最近邻分类器选出人脸最优分类类别并计算识别率。在 ORL人脸库上的实验表明,在人脸图像分辨率下降到(12×10)时,本 文算法的识别率仍能达 到85.00%,基本满足了实际运用中对识别率的要求,并且降低了运算 时间。     

Noise Threshold for Universality of Two-Input Gates

It is known that epsi-noisy gates with two inputs are universal for arbitrary computation (i.e., can compute any function with bounded error), if all gates fail independently with probability epsi and epsi < beta₂ = (3 - radic7)/4 ap 8.856%. In this paper, it is shown that this bound is tight for formulas, by proving that gates with two inputs, in which each gate fails with probability at least beta₂ cannot be universal. Hence, there is a threshold on the tolerable noise for formulas with two-input gates and it is beta₂. It is conjectured that the same threshold also holds for circuits.     

一种支持H.264High Profile的高效可重构反变换VLSI结构

本文针对H.264 Fidelity Range Extensions(FRExt,High Profile)解码过程中扩展的所有变换,采用二维矩阵分解和基于矩阵运算提取公共因子的操作,利用通用运算单元来设计高效的可重构VLSI结构.该结构不但节省面积(可重构变换结构只消耗了4807门电路),并且具有高性能(采用TSM...