Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.     

Analog performance of double gate junctionless tunnel field effect transistor

For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor （DG-JLTFET） and the results are compared with the conventional n-type double gate tunnel field effect transistor （DG-TFET） counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.     

Improved performance of nanoscale junctionless transistor based on gate engineering approach

In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (G_m), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.     

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor(DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO₂. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.     

A bilayer graphene nanoribbon field-effect transistor with a dual-material gate

This paper introduces dual-material gate (DMG) configuration on a bilayer graphene nanoribbon field-effect transistor (BLGNRFET). Its device characteristics based on nonequilibrium Green׳s function (NEGF) are explored and compared with a conventional single-material gate BLGNRFET. Results reveal that an on-off ratio of up to 10 is achievable as a consequence of both higher saturation and lower leakage currents. The advantages of our proposed DMG structure mainly lie in higher carrier transport efficiency by means of enhancing initial acceleration of incoming carriers in the channel region and the suppression of short channel effects. Drain-induced barrier lowering, subthreshold swing and hot electron effect as the key short channel parameters have been improved in the DMG-based BLGNRFET.     

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET(HD_DMG_DLTFET). It is compared with conventional doping-less TFET(DLTFET) and dual material gate doping-less TFET(DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current(I_ON=94 μA/μm), I_ON/I_OFF(≈ 1:36×10¹³), point(≈ 3 mV/dec) and average subthreshold slope(AV-SS=40.40 mV/dec). The proposed device offers low total gate capacitance(C_gg)along with higher drive current. However, with a better transconductance(g_m) and cut-off frequency(f_T), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage(V_EA) and output conductance(g_d) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.     

Impact of gate metal work-function engineering for enhancement of subthreshold analog/RF performance of underlap dual material gate DG-FET

This work presents a systematic comparative study of analog/RF performance for underlap dual material gate (U-DMG) DG NMOSFET. In previous works, improved device performances have been achieved by use of high dielectric constant (k) spacer material. Although high-k spacers improve device performance, the intrinsic gain of the device reduces. For the analog circuits applications intrinsic gain is an important parameter. Hence, an optimized spacer material having dielectric constant, k = 7.5 has been used in this study and the gain is improved further by dual-material gate (DMG) technology. In this paper we have also studied the effect of gate material having different work function on the U-DMG DG NMOSFETs. This device exploits a step function type channel potential created by DMG for performance improvement. Different parameters such as the transconductance (g_m), the gain per unit current (g_m/I_ds), the intrinsic gain (g_mR_o), the intrinsic capacitance, the intrinsic resistance, the transport delay and, the inductance of the device have been analyzed for analog and RF performance analysis. Analysis suggested that the average intrinsic gain, g_m/I_d and g_m are increase by 22.988%, 16.10% and 27.871% respectively compared to the underlap single-material gate U-DG NMOSFET.     

Improvement on the noise performance of InAs-based HEMTs with gate sinking technology

Improvement on the RF and noise performance for 80 nm InAs/In_0.7Ga_0.3As high-electron mobility transistor (HEMT) through gate sinking technology is presented. After gate sinking at 250 °C for 3 min, the device exhibited a high transconductance of 1900 mS/mm at a drain bias of 0.5 V with 1066 mA/mm drain-source saturation current. A current-gain cutoff frequency (f_T) of 113 GHz and a maximum oscillation frequency (f_max) of 110 GHz were achieved at extremely low drain bias of 0.1 V. The 0.08 × 40 μm² device with gate sinking demonstrated 0.82 dB minimum noise figure and 14 dB associated gain at 17 GHz with only 1.14 mW DC power consumption. Significant improvement in RF and noise performance was mainly attributed to the reduction of gate-to-channel distance together with the parasitic source resistance through gate sinking technology.     

Analysis and impact of process variability on performance of junctionless double gate VeSFET

This paper presents an in-depth analysis of junctionless double gate vertical slit FET (JLDG VeSFET) device under process variability. It has been observed that junctionless FETs (JLDG VeSFET) are significantly less sensitive to many process parameter variations due to their inherent device structure and geometric properties. Sensitivity analysis reveals that the slit width, oxide thickness, radius of the device, gate length and channel doping concentration imperceptibly affect the device performance of JLDG VeSFET in terms of variation in threshold voltage, on current, off current and subthreshold slope (Ssub) as compared to its junction based counterpart i.e. MOSFET, because various short channel effects are well controlled in this device. The maximum variation in off current for JLDG VeSFET due to variation in different devices parameters is 5.6% whereas this variation is 38.8% for the MOS junction based device. However, variation in doping concentration in the channel region displays a small deviation in the threshold voltage and on current characteristics of the MOSFET device as compared to JL DG VeSFET.     

Design,modelling, and simulation of a floating gate transistor with a novel security feature

This study proposes a new generation of floating gate transistors (FGT) with a novel built-in security feature. The new device has applications in guarding the IC chips against the current reverse engineering techniques, including scanning capacitance microscopy (SCM). The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate, even in nano-meter scales. The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate. This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic. Furthermore, this model was verified with a simulation. In addition, the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor. The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated. Finally, the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT.     

基于SOA-XGM效应的双逻辑门叠加结构研究

为了提高光传输系统数据信息的机密性与安全性,开展了光传输系统物理层全光加/解密技术的理论分析,设计了全光AB逻辑实验方案,通过结构相同的两全光AB逻辑门输出信号的耦合,实验实现了对速率为10Gb/s的明文光信号的全光加密。     

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature.In this work,first,the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters.The adjusted parameters are ratio of gate and intrinsic length,gate dielectric thickness and gate work function.Secondly,the DMG (dual material gate) DG-IMOS is proposed and investigated.This DMG DG-IMOS is further optimized to obtain the best possible performance parameters.Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS,shows better ION,ION/IOFF ratio,and RF parameters.Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS,optimized performance is achieved including ION/IoFF ratio of 2.87 × 109 A/μm with ION as 11.87 × 10-4 A/μm and transconductance of 1.06 × 10-3 S/μm.It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.     

栅缓冲层对4H碳化硅肖特基势垒场效应晶体管性能的影响

通过在栅极和沟道层间插入一层低掺杂的缓冲层研究了其对肖特基势垒场效应晶体管性能的影响。通过求解一维和二维泊松方程,得到了电流和小信号参数与缓冲层厚度和浓度的依赖关系。当缓冲层厚度为0.15μm时,计算了器件的直流和交流特性;同时仿真了器件的击穿特性。结果表明,电流随缓冲层厚度增加;击穿电压由125V增加到160V;截止频率由20GHz增加到27GHz。     

A study on the electrical characteristics of InGaZnO thin-film transistor with HfLaO gate dielectric annealed in different gases

The effects of dielectric-annealing gas (O₂, N₂ and NH₃) on the electrical characteristics of amorphous InGaZnO thin-film transistor with HfLaO gate dielectric are studied in-depth, and improvements in device performance by the dielectric annealing are observed for each gas. Among the samples, the N₂-annealed sample has a high saturation carrier mobility of 35.1 cm²/V s, the lowest subthreshold swing of 0.206 V/dec and a negligible hysteresis. On the contrary, the O₂-annealed sample shows poorer performance (e.g. saturation carrier mobility of 15.7 cm²/V s, larger threshold voltage, larger subthreshold swing of 0.231 V/dec and larger hysteresis), which is due to the decrease of electron concentration in InGaZnO associated with the filling of oxygen vacancies by oxygen atoms. Furthermore, the NH₃-annealed sample displays the lowest threshold voltage (1.95 V), which is attributed to the increased gate-oxide capacitance and introduced positive oxide charges. This sample also reveals a change in the dominant trap type due to the over-reduction of acceptor-like border and interface traps, as demonstrated by a hysteresis phenomenon in the opposite direction. Lastly, the low-frequency noise of the samples has also been studied to support the analysis based on their electrical characteristics.     

Influence of low-field-mobility-related issues on SiC metal-semiconductor field-effect transistor performance

High field-dependent electron transport characteristics in 4H-SiC were measured successfully using a nanosecond-pulsed technique. It should be noted that the velocity-field characteristics of SiC are different from GaAs in that SiC does not have velocity overshooting behavior. Without the overshooting behavior, the current density of SiC metal-semiconductor field-effect transistors (MESFETs) is restricted fundamentally by the low drift velocity in the low-field, parasitic regions. These parasitic regions not only limit the current density but also are responsible for a significant shift of the threshold voltage.     

埋栅结构双极型静电感应晶体管动态特性的改善

双极型静电感应晶体管(BSIT)的失效经常出现在阻断态与导通态之间的瞬态过渡过程。因此,研究BSIT的开关动态过程的物理机理对于设计和制造高性能器件有着重要意义。本文深入研究了埋栅结构电力BSIT瞬态过程的动态特性,讨论了材料、几何结构与工艺参数对BSIT动态性能的影响。提出了一系列改善BSIT动态特性的工艺措施。     

Improvement on the dynamical performance of a power bipolar static induction transistor with a buried gate structure

The failure of a bipolar static induction transistor(BSIT) often occurs in the transient process between the conducting-state and the blocking-state,so a profound understanding of the physical mechanism of the switching process is of significance for designing and fabricating perfect devices.The dynamical characteristics of the transient process between conducting-state and blocking-state BSITs are represented in detail in this paper.The influences of material,structural and technological parameters on the dynamical performances of BSITs are discussed. The mechanism underlying the transient conversion process is analyzed in depth.The technological approaches are developed to improve the dynamical characteristics of BSITs.     

Impact of gate material engineering(GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation

In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack Schottky-Barrier Source/Drain Gate All Around (SM-GS-SB-S/D GAA) structures are proposed for low- power wireless applications. The Analog/RF performance for wireless applications of these devices are demonstrated. The effect of Schottky-Barrier (Metal) S/D is studied for Single Metal (SM)–SB-GAA, (Dual Metal) DM-SB-GAA, SM-GS-SB-GAA and GME-GS-SB-GAA MOSFETs, and it is found that GME-GS-SB-GAA MOSFET with metal drain source shows much improved performance in terms of transconductance (g_m), output conductance (g_d), Early Voltage (V_EA), Maximum Transducer Power Gain, cut-off frequency (f_T), and I_on/I_off ratio. Further, harmonic distortion for wireless applications is also studied using ATLAS-3D device simulator. Due to low parasitic S/D resistance the metal Source/Drain DM-GS-SB-S/D-GAA MOSFET demonstrates remarkable I_on of~31.8 μA/μm and saturation transconductance g_m of~68.2 μS with improved third order derivative of transconductance g_m3.     

Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects

In this report we focus on the performance of nanoscale double gate (DG) junctionless (JL) and inversion mode (IM) MOSFETs. The study is performed using an analytical 2-D modeling approach from our previous work and an extension for the inclusion of carrier quantization effects (QEs). The model itself is physics-based, predictive and valid in all operating regimes. Important device metrics such as the drain-induced barrier lowering (DIBL), subthreshold slope (S  ) and the _Ion/_Ioff$I_{\mathit{on}}/I_{\mathit{off}}$ ratios are in focus and discussed. The model is compared versus 2-D numerical simulation results from TCAD Sentaurus. To stand the pace with recent ITRS requirements for future CMOS technology, we target devices with a minimum channel length of 16 nm and channel thicknesses down to 3 nm. The purpose of the research is to gain knowledge about the device?s performance at such aggressively scaled dimensions.