基于软件体系结构的测试路径生成方法

在软件体系结构描述语言Wright的基础上,提出了基于软件体系结构的测试覆盖准则及BG动态行为图,根据BG图构造基于覆盖准则的测试路径,生成测试数据。由此平衡开发成本、进度与质量需求之间的关系,最后以Server/Client结构为例说明该方法是适用的。     

Overcoming untuned radios in wireless networks with network coding

The drive toward the implementation and massive deployment of wireless sensor networks calls for ultralow-cost and low-power nodes. While the digital subsystems of the nodes are still following Moore's Law, there is no such trend regarding the performance of analog components. This work proposes a fully integrated architecture of both digital and analog components (including local oscillator) that offers significant reduction in cost, size, and overall power consumption of the node. Even though such a radical architecture cannot offer the reliable tuning of standard designs, it is shown that by using random network coding, a dense network of such nodes can achieve throughput linear in the number of channels available for communication. Moreover, the ratio of the achievable throughput of the untuned network to the throughput of a tuned network with perfect coordination is shown to be close to 1/e. This work uses network coding to leverage the fact that throughput equal to the max-flow in a graph is achievable even if the topology is not know a priori. However, the challenge here is finding the max-flow of the random graph corresponding to the network.     

Powering Internet with power-law networking

It is generally recognized that the current routing scheme of Internet suffers from serious scalability problems. In this paper, we work with the abstract but ??Internet-like?? network model consisting of an infinite-variance power-law random graph (IVPLRG). We adopt the idea of a routing scheme proposed by Carmi, Cohen and Dolev (C-C-D). The scheme fits very naturally to the spontaneously emerging ??soft hierarchy?? architecture on an IVPLRG. The use of multiple addresses is suggested as a solution to the inflexibility of the pure C-C-D scheme. A mean-field approximation is introduced for efficient computation of relevant quantitative characteristics and applied to various problems of our scheme. We review a few recent Internet routing proposals and discuss their relation to our scheme. We find out that the topology creation of our scheme offers advantages in terms of scalability and routing policy control.     

A circuit design of intelligent cache DRAM with automaticwrite-back capability

An intelligent cache based on a distributed architecture that consists of a hierarchy of three memory sections-DRAM (dynamic RAM), SRAM (static RAM), and CAM (content addressable memory) as an on-chip tag-is reported. The test device of the memory core is fabricated in a 0.6 μm double-metal CMOS standard DRAM process, and the CAM matrix and control logic are embedded in the array. The array architecture can be applied to 16-Mb DRAM with less than 12% of the chip overhead. In addition to the tag, the array embedded CAM matrix supports a write-back function that provides a short read/write cycle time. The cache DRAM also has pin compatibility with address nonmultiplexed memories. By achieving a reasonable hit ratio (90%), this cache DRAM provides a high-performance intelligent main memory with a 12 ns(hit)/34 ns(average) cycle time and 55 mA (at 25 MHz) operating current     

激光超声结合CNN的铸件缺陷检测方法

检测金属铸件在工程和使用过程中可能存在的缺陷,应用基于热弹机制的激光超声可视化检测仪对铸件进行扫描并将信号制成最大振幅图像,实现对铸件的可视化检测。为了高效、快速地对最大振幅图进行批量处理,结合卷积神经网络图像处理技术对最大振幅图进行识别。针对任务需要设计了一个卷积神经网络架构对最大振幅图进行识别,识别过程中通过改变卷积层和卷积核大小设置了不同的卷积神经网络架构,将预先设计的架构与其他的架构进行横向对比,实验结果表明预设架构综合性能最好。相同实验条件下,该卷积神经网络架构为使用最大振幅图检测铸件缺陷提供了一个有效可行的方案。     

Design of a 43-Gb/s line terminal based on optical transport network system architecture

The optical transport network (OTN) based on 43-Gb/s channels is expected to be the carriers' next-generation core network. This paper discusses its system architecture, from the requirements of services, protection, and management, and shows a feasible scenario to ensure the rapid penetration of the 43-Gb/s-based OTN. It also describes the design concept and functions of the first 43-Gb/s OTN line terminal. The line terminal deploys time-division multiplexing to handle client signals and provides high-quality, multiple transparent services, such as synchronous optical network/synchronous digital hierarchy and gigabit Ethernet. The configuration and features of the actual fabricated system are described.     

Survivability and reliability of a composite-star transport network with disconnected core switches

This paper deals with the design and dimensioning of a novel survivable optical network structure, called Petaweb, that can reach a total capacity of several Pb/s (10¹⁵ bit/s). The Petaweb has a composite-star architecture that allows two-hop connections between edge nodes through disconnected core nodes. Prior studies of the same authors have tackled the optimization of a Petaweb network architecture with regular and quasi-regular topologies. In this paper, reliability and survivability issues are addressed by introducing a dedicated path protection strategy into the design model. We present by extensive numerical results the reliability and survivability properties of the Petaweb core architecture with respect to single fiber link, core node, or switching plane failure and to switching site disconnection.     

电台软件架构发展及其向SCA4．0演进的途径分析

使用标准的软件架构能够实现波形应用的硬件无关设计,也便于电台软件走向分层开放的合作设计。采用软件通信体系结构SCA,能够实现电台软件的标准化、平台化、智能化。首先对SCA在国内外的发展与应用现状进行了介绍,在基于主流的SCA2．2规范进行的SCA电台软件开发经验的基础上,探讨了SCA4．0架构的特点,提出了把核心框架、平台、波形从SCA2．2架构升级到SCA4．0架构的途径,思考了基于SCA架构的电台软件未来发展趋势。     

一种表达式粒度可重构阵列的VLSI架构及应用

提出一种表达式粒度可重构阵列的VLSI架构,主要面向具有高计算密集度和高数据并行度的应用,如视频编解码.每个处理单元内部包含4个异构数据通路单元,能够映射一个运算表达式,处理单元之间采用三层互联结构.阵列内部包括128位带宽的数据存储模块,具有数据乱序分发和拼接能力,核心计算循环能够映射到可重构阵列上执行.对包含16个处理单元的架构原型进行建模,采用TSMC 90nm工艺综合,工作频率达100MHz,芯片面积为1.38mm2.对2D-DCT算法进行性能比较,结果显示该架构具有更好的计算资源利用率和面积效率.     

A computer-aided approach to the structural analysis and modification of a large circulatory system model

The purpose of this study is to show an approach to making an intelligent support system for understanding and modifying a large circulatory system model using techniques of system analysis. Structural analysis makes it possible to visualize hierarchies of Coleman's circulatory model Human. Two techniques are successively applied for structural analysis, model reduction and graph analysis by interpretative structural modeling (ISM). First, the analysis for model reduction removes input-output relations with an input-output gain less than a given threshold, and second, the ISM technique applied to the reduced model of Human provides hierarchical directed graphs. The proposed approach: 1) enables visualization of a hierarchy graph of cause and effect relations of the large circulatory model, 2) suggests control and diagnostic information to the model by tracing back a path in the hierarchy, and 3) allows the user to modify the circulatory model. The efficiency and performance of the proposed approach demonstrates technical indications of success in analyzing and justifying experimental evidences with the online help of the system.     

一种高性能低功耗微控制器的设计

阐述了一种高性能低功耗MCU的设计。谊MCU和标准8051具有相同的指令系统和功能，通过体系结构上釆用哈佛结构、1时钟机器周期和指令预取，提高MCU的工作效率；利用门控时钟，降低MCU的功耗。在CPU内部模块上，设计了独立于ALU的乘除法模块、并行执行结构ALU、多时钟体系状态机，以提高MCU的速度，从而达到优于标准8051的性能．釆用所设计的MCUIP核，成功地在Altera的APEX20K上通过FPGA仿真，谊器件可方便地运用于片上系统(SOC)。     

A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM

A CMOS EDGE baseband and multimedia handset SoC features a dual core (microcontroller and DSP) architecture together with all the necessary interface logic and hardware accelerators interconnected by a multi-layer bus. The DSP memory hierarchy features an instruction cache coupled to a 6-Mbit embedded DRAM instruction memory allowing in the field software flexibility (for example dynamic upgrade of DSP software), while minimizing power and area (closely matching a ROM based solution). The chip is implemented in a 130-nm 6-metal layer CMOS process and is packaged in a 12 /spl times/ 12 ball-grid array. Full chip standby mode current is 690 /spl mu/A (with data retention), resulting in a 500 hour complete GSM/EDGE terminal autonomy.     

Efficient variable partitioning and scheduling for DSP processors with multiple memory modules

Multiple on-chip memory modules are attractive to many high-performance digital signal processing (DSP) applications. This architectural feature supports higher memory bandwidth by allowing multiple data memory accesses to be executed in parallel. However, making effective use of multiple memory modules remains difficult. The performance gain in this kind of architecture strongly depends on variable partitioning and scheduling techniques. In this paper, we propose a graph model known as the variable independence graph (VIG) and algorithms to tackle the variable partitioning problem. Our results show that VIG is more effective than interference graph for solving variable partitioning problem. Then, we present a scheduling algorithm known as the rotation scheduling with variable repartition (RSVR) to improve the schedule lengths efficiently on a multiple memory module architecture. This algorithm adjusts the variable partitions during scheduling and generates a compact schedule based on retiming and software pipelining. The experimental results show that the average improvement on schedule lengths is 44.8% by using RSVR with VIG. We also propose a design space exploration algorithm using RSVR to find the minimum number of memory modules and functional units satisfying a schedule length requirement. The algorithm produces more feasible solutions with equal or fewer number of functional units compared with the method using interference graph.     

Research of novel complex optical network routing architecture

This article puts forward a novel routing architecture for complex optical network,which core component is path calculation element(PCE).As is well known,the PCE-based distributed path computation structure is making the routing control and computation loosely coupled from traditional control plane.In the study,the resource allocation and routing algorithm are the critical part of PCE hierarchy.To compare the performance of new architecture and the traditional one,the user uses the flooding suppression,routing delay,resource utilization and traffic blocking probability as performance simulation parameters and taking the verification simulation on objective modular network testbed(OMNeT)platform against to source-node routing architecture.The numerical analysis,computer simulation and experiment work indicate that the operation of PCE-based routing architecture can reduce the flooding information of path calculation request as well as the routing hops significantly and improve the quality of service(QoS)by decreasing the blocking probability when failure happened.     

一种软件体系结构级测试序列生成技术

软件体系结构(software architecture,SA)通过对系统构件及其交互的抽象,提供了一个描述大型、复杂系统的高层次模型,软件体系结构的动态描述常被用来指导分析和测试.本文通过CHAM(chemical abstract ma-chine,CHAM)描述的SA规格说明生成LTS,并根据测试需求进行测试功能的选取,提出了基于功能的最小LTS图(M-LTS)生成方法,根据McCabe覆盖方法生成M-LTS图的测试路径.最后以B/S结构为例,验证了该方法在生成SA级的测试路径上是可行的.     

融合锚词抽取的海量短文本主题层次挖掘

从短文本集中挖掘不同粒度的主题、构建主题的层次结构在舆情分析、视觉检测、语义挖掘和图谱构建等方面具有重要应用.围绕如何从短文本集中分层次地挖掘主题,在修改传统短语定义的基础上,提出了融合锚词抽取的海量短文本主题层次挖掘框架.提出的主题层次挖掘框架首先基于词共现图实现主题推断和锚词抽取;然后,应用关联规则挖掘频繁锚词短语;最后,采用排序方法量化锚词短语以寻找最具代表性的主题短语.与已有的基于词共现图构建主题层次的方法相比,融合了锚词抽取的词共现图分析方法更有利于构建层次更高的主题.在2个实际的中文短文本数据集上执行实验,结果表明提出的方法挖掘的短语能较好地解释主题和用于分类预测.     

Packet Processing acceleration with a 3-stage programmable pipeline engine

In this letter, we present the architecture and implementation of a novel, 3-stage processing engine, suitable for deep packet processing in high-speed networks. The engine, which has been fabricated as part of a network processor, comprises of a typical RISC core and programmable hardware. To assess the performance of the engine, experiments with packets of various lengths have been performed and compared against the IXP1200 network processor. The comparison has revealed that for the case study shown in this letter, the proposed packet-processing engine is up to three times faster. Moreover, the engine is simple to be fabricated, less expensive than the corresponding hardware cores of IXP1200 and can be easily programmed for different networking applications.     

Bipartite graph design principle for photonic switching systems

Several attributes of a bipartite graph are exploited in designing switching systems. First, in a network based on bipartite graphs, no two paths are allowed to intersect at a vertex. This attribute is used to design a directional coupler-based photonic switching network with very low crosstalk. Since crosstalk is the most limiting factor in constructing a large directional-coupler-based photonic switching network, crosstalk reduction on the device and architecture levels is an important design issue. Secondly, broadcast, which is an intrinsic property of a bipartite graph (the same is always true with a crossbar representation), is used in designing multiconnection switching networks. Thirdly, it is shown that the nonplanar nature of bipartite graphs makes them well suited for designing three-dimensional free-space-transmission photonic switching systems     

融合量子密钥分配的电信运营商密码应用体系

基于量子密钥分配（quantum key distribution,QKD）的通信网络具备实现“perfect secrecy”（完美保密性）的能力，当前还不能满足大规模应用的需求，在实际应用中需要结合经典密码技术。提出了融合量子密钥分配的电信运营商密码应用体系的功能架构模型，介绍了模型的层次结构、核心的网元和功能模块以及接口关系，给出了应用体系的整体框架，介绍了框架的主要组成部分，描述了应用体系的典型应用场景及其工作流程。     

VLSI architecture for a low-power video codec system

In this paper, the design of a very large scale integration (VLSI) architecture for low-power H.263/MPEG-4 video codec is addressed. Starting from a high-level system modelling, a profiling analysis indicates a hardware–software (HW–SW) partitioning assuming power consumption, flexibility and circuit complexity as main cost functions. The architecture is based on a reduced instruction set computer engine, enhanced by dedicated hardware processing, with a memory hierarchy organisation and direct memory access-based data transfers. To reduce the system power consumption two main strategies have been adopted. The first consists in the design of a low-power high-efficiency motion estimator specifically targeted to low bit-rate applications. Exploiting the correlation of video motion field it attains the same high coding efficiency of the full-search approach for a computational burden lower than about two orders of magnitude. Combining the decreased algorithm complexity with low-power VLSI design techniques the motion estimator power consumption is scaled down to few mW. The second consists in the implementation of a proper buffer hierarchy to reduce memory and bus power consumption in the HW–SW communication. The effectiveness of the proposed architecture has been validated through performance measurements on a prototyping platform.