Symmetry relations in multidimensional Fourier transform pairs

A relation between the types of symmetries that exist in signal and Fourier transform domain representations is derived for continuous as well as discrete domain signals. The symmetry is expressed by a set of parameters, and the relations derived in this paper will help to find the parameters of a symmetry in the signal or transform domain resulting from a given symmetry in the transform or signal domain respectively. A duality among the relations governing the conversion of the parameters of symmetry in the two domains is also brought to light. The application of the relations is illustrated by a number of two-dimensional examples.Notation R the set of real numbers - R ^m R × R × ... × R m-dimensional real vector space - continuous domain real vector - L {¦ – _i , i = 1,2,..., m} - m-dimensional frequency vector - W { – _i ,i=1,2,..., m} - m-dimensional normalized frequency vector - _P {¦ – _i , i=1,2,...,m} - g(ol) g (₁,₂,..., _m ) continuous domain signal - () ( _{1 2},..., _m )=G (j ₁,j ₂,..., j _m ) Fourier transform ofg (ol) - (A,b,,,) parameters ofT- symmetry - N the set of integers - N ^m N × N × ... × N m-dimensional integer vector spacem-dimensional lattice - h(n) h (n ₁,.,n _m ) discrete domain signal - H() Fourier transform ofh (n) - v ₁,v ₂,..., v_m m sample-direction and interval vectors - V (v ₁ v ₂ ...v _m ) sampling basis matrix - [x]^* complex conjugate ofx - detA determinant ofA - X {x¦ – x _i , i=1,2,..., m} - A ^–t [A ^–1] ^t ,t stands for transpose This work was supported in part by the Natural Sciences and Engineering Research Council of Canada under Grant A-7739 to M. N. S. Swamy and in part by Tennessee Technological University under its Faculty Research support program to P. K. Rajan.     

Gaussian radial basis functions and inner product spaces

An approximation result is given concerning Gaussian radial basis functions in a general inner product space. Applications are described concerning the classification of the elements of disjoint sets of signals, and also the approximation of continuous real functions defined on all of ⁿ using radial basis function (RBF) networks. More specifically, it is shown that an important large class of classification problems involving signals can be solved using a structure consisting of only a generalized RBF network followed by a quantizer. It is also shown that Gaussian radial basis functions defined on ⁿ can uniformly approximate arbitrarily well over all of ⁿ any continuous real functionalf on ⁿ that meets the condition that |f(x)|0 as x.     

Testing for Function and Performance: Towards an Integrated Processor Validation Methodology

Microprocessor design teams use a combination of simulation-based and formal verification techniques to validate the pre-silicon models prior to tape-out and chip fabrication. Pseudo-random test case generation to cover the architectural space is still relied upon as the principal means to identify design bugs. However, such methods are limited to functional bugs only. Detection and diagnosis of timing (performance) bugs at the architectural level is largely an expert job. Architects guide the performance team to run manually generated test cases to validate the design from a performance viewpoint. In this paper, we will review some of the new approaches being tried out to automate the generation of performance test cases. We will show how this can be done within the basic framework of current functional validation and testing of pre-silicon processor models. Three categories of reference specifications are used in determining the defect-free pipeline timing behavior associated with generated test cases: (a) axiomatic specifications of intrinsic machine latencies and bandwidths; (b) proven analytical models for simple basic block and loop test cases; and, (c) a stable reference behavioral/functional (pre-RTL) model of the processor under development. We report experimental results obtained in performance validation studies applied to real PowerPC processor development projects.     

The discrete Einstein relation

In this paper the connection between massM, resistance and commute time for random walks on graphs is further explored, and the relation=2M · is proved. An extension of the result is made to multigraphs, which are an extension of the graph concept where a black box is treated like an edge.     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

A scalable wireless virtual LAN

This paper presents a Wireless Virtual Local Area Network (WVLAN) to support mobility in IPoverATM local area networks. Mobility is handled by a joint ATMlayer handoff for connection rerouting and MAClayer handoff for location tracking, such that the effects of mobility are localized and transparent to the higherlayer protocols. Different functions, such as Address Resolution Protocol (ARP), mobile location, and ATM connection admission are combined to reduce protocol overhead and frontend delay for connectionless packet transmission in connectionoriented ATM networks. The proposed WVLAN, through the use of ATM technology, provides a scalable wireless virtual LAN solution for IP mobile hosts.     

Linear phase FIR approximation of magnitude response |1/ω| for maximal flatness at an arbitrary frequency ω0, 0<ω0<π*

In many signal processing situations, the desired (ideal) magnitude response of the filter is a rational function: (a digital integrator). The requirements of a linear phase response and guaranteed stable performance limit the design to a finite impulse response (FIR) structure. In many applications we require the FIR filter to yield a highly accurate magnitude response for a narrow band of frequencies with maximal flatness at an arbitrary frequency ₀ in the spectrum (0, ). No techniques for meeting such requirements with respect to approximation of are known in the literature. This paper suggests a design by which the linear phase magnitude response can be approximated by an FIR configuration giving a maximally flat (in the Butterworth sense) response at an arbitrary frequency ₀, 0<₀<^*. A technique to compute exact weights for the design has also been given.     

An adaptive algorithm for optimizing the packet size used in wireless ARQ protocols

We develop an algorithm that allows an ARQ protocol to dynamically optimize the packet size based on estimates of the channel biterrorrate. Our algorithm is particularly useful for wireless and satellite channels where the biterrorrates tend to be relatively high and time variable. Our algorithm uses the acknowledgment history to make estimates of the channel biterrorrate, based on which the optimal packet size can be chosen. We develop a Markov chain model for the analysis of the system, under static channel conditions, and show that the algorithm can achieve close to optimal performance using a history of just 10,000 bits. We also use the Gilbert–Elliott twostate Markov channel to model dynamic channel conditions. We show, through simulation, that the algorithm performs well even under rapidly changing channel conditions. Finally, we discuss a maximum likelihood approach for choosing the packet size, which performs almost optimally but is much easier to implement.     

Dynamic capacity allocation and hybrid multiplexing techniques for ATM wireless LANs

We consider digital wireless multimedia LANs and timevarying traffic rates. To deal effectively with the dynamics of the timevarying traffic rates, a Traffic Monitoring Algorithm (TMA) is deployed to dynamically allocate channel capacities to the heterogeneous traffics. The TMA is implemented as a higher level protocol that dictates the capacity boundaries within two distinct framed transmission techniques: a Framed Time DomainBased (FTDB) technique and a Framed CDMA (FCDMA) technique. The performance of the TMA in the presence of the FTDB technique is compared to its performance in the presence of the FCDMA technique for some traffic scenarios. The performance metrics used for the TMAFTDB and TMAFCDMA combinations are channel capacity utilization factors, traffic rejection rates, and traffic delays. It is found that the TMAFTDB is superior to the TMAFCDMA when the speed of the transmission links is relatively low and the lengths of the transmitted messages are relatively short. As the speed of the transmission links and the length of the transmitted messages increase, the TMAFCDMA eventually outperforms the TMAFTDB.     

Routing with multiple QoS requirements for supporting multimedia applications

Distributed multimedia applications usually require multiple QoS performance guarantees. However, in general, searching such a route in the network, to support multimedia applications, is known to be NPcomplete. In this paper, we propose a new heuristic QoS routing algorithm, called QoSR_DKS, for supporting multimedia applications in highspeed networks. QoSR_DKS is a modification of rulebased Fallback routing and Dijkstra algorithms. It can search a unicast route that would have enough network resources so that multiple QoS requirements (bandwidth, delay, and delay jitter) of the requested flow could be guaranteed. Its worst case computation time complexity is the same as that of the Dijkstra algorithm, i.e., O(V²), where V is the number of nodes in the network. Extensive simulations were done with various network sizes, upto 500 nodes networks, where each node uses Weighted Fair Queueing (WFQ) service discipline. Results show that QoSR_DKS is very efficient. It could always find the QoS satisfying route, whenever there exists one (success rate is optimal), and its average computation time is near to simple shortest path Dijkstra algorithm.     

Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation

This paper presents a methodology for characterizing the random component of transistor mismatch in CMOS technologies. The methodology is based on the design of a special purpose chip which allows automatic characterization of arrays of NMOS and PMOS transistors of different sizes. Up to 30 different transistor sizes were implemented in the same chip, with varying transistors width W and length L. A simple strong inversion large signal transistor model is considered, and a new five parameters MOS mismatch model is introduced. The current mismatch between two identical transistors is characterized by the mismatch in their respective current gain factors /, V _TO threshold voltages , bulk threshold parameters , and two components for the mobility degradation parameter mismatch ₀ and _e. These two components modulate the mismatch contribution differently, depending on whether the transistors are biased in ohmic or in saturation region. Using this five parameter mismatch model, an extraordinary fit between experimental and computed mismatch is obtained, including minimum length (1 m) transistors for both ohmic and saturation regions. Standard deviations for these five parameters are obtained as well as their respective correlation coefficients, and are fitted to two dimensional surfaces f(W, L) so that their values can be predicted as a function of transistor sizes. These functions are used in an electrical circuit simulator (Hspice) to predict transistor mismatch. Measured and simulated data are in excellent agreement.     

On the design of feedback controllers to achieve prescribed initial value constraints

The problem of designing a stabilizing compensator for a control system to achieve prescribed initial value constraints ⁽ⁱ⁾(0⁺)=y_i is considered. Indeed, modulo certain technical conditions, such a compensator exists if and only if y_i=0;i= 0,1,...,rp +rt –2; whererp is the relative degree of the plant andrt is the relative degree of the system input. This theorem is derived and a complete parameterization of the set of compensators that achieve the prescribed design constraints is formulated.This research was supported in part by NSF Grant No. 921106.     

Long-Term Business Modelling Using System Dynamics

This paper presents an overview of the methodology used to model the resource allocation decisions of a research organisation using system dynamics. The resulting model combined the concept of aging chains and co-flows of System Dynamics with conventional spreadsheet analysis, and included representations of staff development and turnover; patent development and licensing revenue; and revenue from other sources. Using the model, senior management were able to evaluate the impact over the coming years of different resource allocation strategies.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

Digital Technique for Instability Detection and Saturation Recovery in High-Order SC ΣΔ Modulators

Stability and saturation recovery are a key concern in High-order Switched Capacitor (SC) modulators, since they are conditionally stable architectures.A novel digital technique, which allows to detect instability in the digital domain, a fast recover of high-order modulators from instability and guarantees a minimum of Signal-to-Noise Ratio (SNR) also when the architecture gets unstable, is proposed. This technique operates in two steps: first, the instability is detected in the digital domain and the system is recovered to a proper operation and then a digital post-processing is performed in order to achieve a residual SNR also in the instability condition.This strategy has been applied to a 6th-order SC bandpass modulator operating at 42.8 MHz and featuring 74 dB Dynamic Range (DR) in a 200 kHz bandwidth. The benchmark modulator has been integrated in a standard double-poly 0.35 m 3.3 V CMOS technology with five metal layers.     

The prime and generalized nullspaces of right regular pencils

The classical notion of the -generalized nullspace, defined on a matrixA R ^n×n,where is an eigenvalue, is extended to the case of ordered pairs of matrices(F, G), F, G R ^m×nwhere the associated pencilsF – G is right regular. It is shown that for every C {} generalized eigenvalue of (F, G), an ascending nested sequence of spaces {P ⁱ ,i=1, 2,...} and a descending nested sequence of spaces {ie495-02 i=1, 2,...} are defined from the -Toeplitz matrices of (F, G); the first sequence has a maximal elementM ^* , the -generalized nullspace of (F, G), which is the element of the sequence corresponding to the index , the -index of annihilation of (F, G), whereas the second sequence has the first elementP ^* as its maximal element, the -prime space of (F, G). The geometric properties of the {M ⁱ ,i=1, 2,..., and {P ⁱ ,i=1, 2,...sets, as well as their interrelations are investigated and are shown to be intimately related to the existence of nested basis matrices of the nullspaces of the -Toeplitz matrices of (F, G). These nested basis matrices characterize completely the geometry ofM ^* and provide a systematic procedure for the selection of maximal length linearly independent vector chains characterizing the-Segre characteristic of (F, G).     

Predictive Caching Strategy for On-Demand Routing Protocols in Wireless Ad Hoc Networks

Route caching strategy is important in on-demand routing protocols in wireless ad hoc networks. While high routing overhead usually has a significant performance impact in low bandwidth wireless networks, a good route caching strategy can reduce routing overheads by making use of the available route information more efficiently. In this paper, we first study the effects of two cache schemes, link cache and path cache, on the performance of on-demand routing protocols through simulations based on the Dynamic Source Routing (DSR) protocol. Since the path cache DSR has been extensively studied, we focus in this paper on the link cache DSR in combination with timer-based stale link expiry mechanisms. The effects of different link lifetime values on the performance of routing protocol in terms of routing overhead, packet delivery ratio and packet latency are investigated. A caching strategy incorporating adaptive link timeout is then proposed, which aims at tracking the optimal link lifetime under various node mobility levels by adaptively adjusting the link lifetime based on the real link lifetime statistics. The performance of the proposed strategy is then compared with the conventional path cache DSR. The results show that without a timeout mechanism, a link cache scheme may suffer severe performance degradation due to the use of broken routes, while the proposed adaptive link cache strategy achieves significantly improved performance by reducing the routing overhead when the network traffic load is high.     

Pervasive Home Environments

For decades, technologists have been promising the intelligent house. The vision is usually portrayed as a house filled with technology which will do the dweller's bidding and take all domestic drudgery out of their lives. The truly intelligent house is still some way off, but the emergence of broadband, availability of faster, smaller and ever cheaper computing equipment and a variety of wired and wireless network technologies are enabling technologies that bring this vision closer to reality. These technology trends lead to the concept that computing and other smart devices will become pervasive, fully networked and disappear into the infrastructure of the home. People will carry out their tasks unaware of the complexity of the infrastructure that supports their activities in much the same way as people today use mains electricity.This paper introduces these concepts and discusses the technological challenges to be overcome. We present our vision of the pervasive home environment where inhabitants can focus on tasks rather than the technology: I need to create X and send it to Y rather than I need to use this computer and this application which needs access to service A and resource B. Although this sounds simple, the environment needs to understand who I is, and who or what Y is. Appropriate permissions must be in place and resources allocated, if available. The most appropriate interface for the task and user must be determined.The pervasive, intelligent home will make available new ways to access and share information. It will herald new services, such as care and support of people in the home, entertainment, educational and security services. The final part of the paper discusses the commercial opportunities and challenges which must be met, not least the need for industry to agree on open standards and interfaces.     

A Reduced Delay Method for Improving the Performance of Sigma-Delta Analog-to-Digital Converters (ADC)

Excess loop delay in a continuous-time switched-current modulator causes a stability problem and degrades the modulator's dynamic range. This paper presents a simple and effective way to reduce the loop delay and improve the modulator's performance. The loop delay of the ADC is reduced by feeding the predicted next state to the comparator. With reduced loop delay, a larger loop gain is allowed without a stability problem, and hence, the dynamic range of the ADC is improved. A new circuit architecture to realize a second-order modulator with this method is also presented. From the simulation result, the new architecture shows a 6–10 dB improvement in dynamic range for a second-order modulator.