Status and trends of silicon RF technology

The current research and development activities in silicon radio-frequency (RF) technologies are first reviewed, accompanied by an illustration of the most pronounced shortcomings of conventional silicon technology in the integrability of RF functions at high GHz frequencies. In the discussion on active RF devices mainly CMOS is investigated due to great interest in this mass-production technology. Issues related to the integration of spiral inductors on silicon are addressed, stressing in particular the difficulty of RF substrate potential definition. Silicon micromachining techniques are highlighted as potential solutions to the integration of RF passives and to reduce substrate losses and cross-talk on silicon. It is explained that micromachining techniques are the best introduced to the silicon mainstream by using post-processing and minimum process complexity.     

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

Integrated RF architectures in fully-organic SOP technology

Future wireless communications systems require better performance, lower cost, and compact RF front-end footprint. The RF front-end module development and its level of integration are, thus, continuous challenges. In most of the presently used microwave integrated circuit technologies, it is difficult to integrate the passives efficiently with required quality. Another critical obstacle in the design of passive components, which occupy the highest percentage of integrated circuit and circuit board real estate, includes the effort to reduce the module size. These issues can be addressed with multilayer substrate technology. A multilayer organic (MLO)-based process offers the potential as the next generation technology of choice for electronic packaging. It uses a cost effective process, while offering design flexibility and optimized integration due to its multilayer topology. We present the design, model, and measurement data of RF-microwave multilayer transitions and integrated passives implemented in a MLO system on package (SOP) technology. Compact, high Q inductors, and embedded filter designs for wireless module applications are demonstrated for the first time in this technology.     

Design of integrated low noise amplifiers (LNA) using embedded passives in organic substrates

The noise figure of a low noise amplifier (LNA) is a function of the quality factor of its inductors. The lack of high-Q inductors in silicon has prevented the development of completely integrated complementary metal oxide semiconductor (CMOS) LNAs for high sensitivity applications like global system for mobile communications (GSM) (1.9 GHz) and wideband code-division multiple-access (W-CDMA) (2.1GHz). Recent developments in the design of high-Q inductors (embedded in low cost integrated circuit (IC) packages) have made single-package integration of RF front-ends feasible. These embedded passives provide a viable alternative to using discrete elements or low-Q on-chip passives, for achieving completely integrated solutions. Compared to on-chip inductors with low Q values and discrete passives with fixed Q/sub s/, the use of these embedded passives also leads to the development of the passive Q as a new variable in circuit design. However, higher Q values also result in new tradeoffs, particularly with respect to device size. This paper presents a novel optimization strategy for the design of completely integrated CMOS LNAs using embedded passives. The tradeoff of higher inductor size for higher Q has been adopted into the LNA design methodology. The paper also presents design issues involved in the use of multiple embedded components in the packaging substrate, particularly with reference to mutual coupling between the passives and reference ground layout.     

Single-package integration of RF blocks for a 5 GHz WLANapplication

Transceivers for future digital telecommunications applications (third generation cellular, wireless LAN) need to be portable (compact), battery-powered and wireless. Today's single-chip solutions for RF front-ends do not yield complete system integration. For example, they typically still need external components for impedance matching, for antenna switches, for power amplifiers and for RF bandpass filters (BPFs). Furthermore, problems of substrate coupling (either manifesting as analog crosstalk or as noise coupling from the digital part to the analog part on mixed-signal chip) become more important with increasing integration. A system-in-a-package (SiP) approach can address these problems. High quality components can be integrated in the package, avoiding lower quality on-chip passives or circumventing expensive chip technology adaptations. Virtually all external components can be integrated, as shown in this paper for the case of the bandpass filters and the impedance matching. Even the antenna is a candidate for integration in the package. Further, a clever chip partitioning can reduce the substrate coupling problem. Partitioning also allows using the best IC-technoiogy for each component. This paper reports on a fully integrated single-package RF prototype module for a 5 GHz WLAN receiver front-end, which is intended to demonstrate the concept of SiP integration. The approach, that is illustrated here with prototype RF blocks for a 5 GHz WLAN application, is implemented with a thin film multichip module (MCM-D) interconnect technology. This technology also allows the integration of high quality passive components. With these passives, low-loss filters can be implemented. The use of passives, filters and off-the-shelf, active, bare die components opens the way to successful system integration     

The partial silicon-on-insulator technology for RF power LDMOSFET devices and on-chip microinductors

A new partial silicon-on-insulator (SOI) formation technology and the associated RF LDMOSFET device structure on a silicon bulk substrate are proposed in this paper. The same technology can also be applied to enhance the quality factor of the integrated on-chip microinductors. The proposed technology is able to reduce both drain/substrate parasitics and leakage current for devices fabricated on bulk substrates. At the same time, the approach overcomes the thermal problem encountered by devices fabricated on full-SOI substrates. To demonstrate the technology, both partial-SOI LDMOSFET and microinductor devices were fabricated on a bulk wafer with their RF performance verified by laboratory measurements.     

A Two-Wafer Approach for Integration of Optical MEMS and Photonics on Silicon Substrate

This letter reports a novel two-wafer approach which demonstrates an integration of optical microelectromechanical system (MEMS) devices and photonics on a silicon substrate. The great advantage of this novel wafer bonding scheme is the ability to maintain the optical axis of the optical MEMS device at the same axis as the optical components. The bonded two wafers which are partially processed, which allows for further processing on the wafer after bonding. Thus, the critical alignment issue is resolved for devices requiring precise alignment in x-/y-/z-axis. Individual functionalities of optical MEMS device and optical coupling between silicon waveguide, fibers and ball lens are demonstrated. This technology shows the potential for integrating silicon photonics integrated circuit and MEMS components with reconfiguration functions on a single silicon substrate.      

CMOS substrate coupling modeling and analysis flow for submicron SoC design

CMOS technology substrate crosstalk modeling and a respective analysis flow that captures the affected circuit performance is described. The proposed methodology can be seamlessly integrated into any industrial Analog/RF circuit design flow, and be compatible within standard design environments. It provides accurate estimation of the substrate coupling effects and can estimate adequately all the mask design level isolation performance trends by adapting an advanced substrate modeling concept based on geometrical and process data. Different substrate model accuracy constraints can be invoked depending on the design phase and the simulation time needs. The provided accuracy is validated by correlating simulation results versus on wafer silicon measurements in a 28 nm CMOS set of ring oscillators with carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV while the error sigma is 765 μV.     

硅基高精度镍铬薄膜电阻的制备和性能表征

集成无源元件（IPD）技术可以将分立的无源元件集成在衬底内部,提高系统的集成度。为了获得高精度的薄膜电阻,采用多层薄膜电路工艺在硅晶圆上制备了不同线宽的镍铬薄膜电阻,利用显微镜和半导体参数测试仪对薄膜电阻的图形线宽及电学特性进行了表征及测试。结果表明,制备出的镍铬薄膜电阻线宽精度在±5%以内,电阻精度在±0.5%以内,具有稳定的电学特性。基于镍铬的高精度硅基无源集成电阻器在系统集成中有广泛的应用价值。     

Surface-passivated high-resistivity silicon as a true microwave substrate

This paper addresses the properties of a surface-passivated (enhanced) high-resistivity silicon (HRS) substrate for use in monolithic microwave technology. The detrimental effects of conductive surface channels and their variations across the wafer related to the local oxide and silicon/silicon-dioxide interface quality are eliminated through the formation of a thin amorphous layer at the wafer surface. Without passivation, it is found that the surface channels greatly degrade the quality of passive components in HRS by masking the excellent properties of the bulk HRS substrate and by causing a spread in parameters and peak values across the wafer. Moreover, it is seen that the surface passivation leads to excellent agreement of the characteristics of fabricated components and circuits with those predicted by electromagnetic (EM) simulation based on the bulk HRS properties. This is experimentally verified for lumped (inductors and transformers) and distributed (coplanar waveguide, Marchand balun) passive microwave components, as well as for a traveling-wave amplifier, through which also the integration of transistors on HRS and the overall parameter control at circuit level are demonstrated. The results in this paper indicate the economically important possibility to transfer microwave circuit designs based on EM simulations directly to the HRS fabrication process, thus avoiding costly redesigns.     

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

Silicon technology has progressed over the last several years from a digitally oriented technology to one well suited for microwave and RF applications at a high level of integration. Technology scaling, both at the transistor and back-end metallization level, has driven this progress. CMOS technology is ideally suited for low-noise amplification and receiver applications, but the fundamental breakdown voltage is lower than that of equivalent Si/SiGe HBTs. High-quality passive devices are equally important, and improvements in metallization technology are resulting in higher quality inductors. This paper summarizes the silicon technology issues associated with RF "system-on-a-chip" applications.     

An enhanced quasi-monolithic integration technology for microwave and millimeter wave applications

A new technology for integration of high frequency active devices into low cost silicon substrate has been introduced. The novel fabrication process gives excellent advantages such as extremely low thermal resistance, and a much lower thermo-mechanical stress than the earlier quasimonolithic integration technology (QMIT) concept . This highly improves the packaging lifetime and electrical characteristics of the active devices. The fabrication process is simple and compatible with fabrication of high-Q passive elements. Successful integration of high-Q passive elements on low resistivity silicon substrate in this technology has been possible for the first time. In comparison to the earlier concept of QMIT, elimination of air-bridges in this technology not only reduces the parasitic elements but also enables the fabrication of the rest of the circuit after measuring the microwave characteristics of the embedded active devices. This makes very accurate microwave and millimeter-wave designs possible. Using the new fabrication process, microwave and millimeter-wave circuits (with both coplanar and microstrip lines) containing power devices have for the first time been possible. Furthermore, the enhanced QMIT can be considered as an organic deposited multi chip module (MCM-D), which is a potential candidate for integration an system on a package (SOP) at microwave and millimeterwave frequencies.     

Weak light effect in multicrystalline silicon solar cells

Minority carrier trapping centers frequently exist in solar grade multicrystalline silicon, such trapping centers cause a drastic increase in photoconductance at carrier injection levels equal to and below the trap density, this phenomenon leads to higher open circuit voltage for multicrystalline silicon solar cells at illumination levels below about 0.2 suns compared to high performance crystalline silicon solar cells. In this paper, the open circuit voltage of multicrystalline silicon solar cells are investigated at low illumination levels, the experiments prove that some multicrystalline silicon solar cells which have higher trap density have higher open circuit voltage at weak illumination levels, and have lower efficiency, so a new method is presented to analyze quality of multicrystalline silicon by measuring open circuit voltage at weak illumination levels in-line, this makes cells manufacturers gain insight into the quality of multicrystalline silicon wafer from different multicrystalline silicon manufacturers easily with the same cell process before screenprinting and firing.     

系统集成中的高阻硅IPD技术

集成无源器件(IPD)技术可以将分立的无源器件集成在衬底内部,提高器件Q值及系统集成度。由于高阻硅衬底具有良好的射频特性,高阻硅IPD技术可以制备出Q值高达70以上的电感。高阻硅IPD基于薄膜技术具有高精度、高集成度等特点,可将无源器件特征尺寸缩小一个数量级。同时可利用成熟的硅工艺平台,便于批量生产降低成本。此外,高阻硅IPD技术可与硅通孔(TSV)技术兼容,可实现三维叠层封装。分析表明,高阻硅IPD技术在系统集成中具有广泛应用前景。     

Chip-package codesign of a low-power 5-GHz RF front end

Future high-performance wireless communication applications such as wireless local area networks (WLANs) around 5 GHz require low-power and highly integrated transceiver solutions. The integration of the RF front end especially poses a great challenge in these applications, as traditional front-end implementations require a large number of external passive components. In this paper, we present the single-package integration of complete transceivers based on a thin-film multichip module (MCM) technology with integrated passives. The MCM substrate is a a common carrier onto which different ICs are mounted. passive components such as RF bandpass filters, inductors, capacitors, and resistors are directly integrated into the MCM substrate with the use of the multilayer structure of the MCM technology. The “system-on-a-package” approach is illustrated with a voltage-controlled oscillator for Digital European Cordless Telephone (DECT) applications and a 5-GHz WLAN front end. These examples indicate that this approach yields a compact low-power implementation of complete transceivers for high-performance wireless applications     

An wide-range tunable on-chip radio-frequency LC-tank formed with a post-CMOS-compatible MEMS fabrication technique

An on-chip-micromachined tunable LC-tank, which consists of a metal inter-digitated variable capacitor and a metal solenoid inductor, is developed for wide-range radio-frequency (RF) tuning in multi-GHz band. A low-temperature metal MEMS process is developed to on-chip fabricate the passives. The process can be used for post-CMOS-compatible integration with RF ICs. Both the varactor and the inductor are suspended with a gap from the low-resistivity silicon wafer (i.e. standard CMOS wafer) for effectively depressing RF loss. The fabricated variable capacitor part, the inductor part and the whole tunable LC resonator are sequentially tested, finally resulting in a wide resonance-frequency tuning range of 72% (between about 3.5 and 6.0 GHz) under a low tuning voltage range of 0-4 V, while the Q-factor ranged within 23 and 8.     

SiGe BiCMOS technology for RF circuit applications

SiGe BiCMOS is reviewed with focus on today's production 0.18-/spl mu/m technology at f/sub T//f/sub MAX/ of 150/200 GHz and future technology where device scaling is bringing about higher f/sub T//f/sub MAX/, as well as lower power consumption, noise figure, and improved large-signal performance at higher levels of integration. High levels of radio frequency (RF) integration are enabled by the availability of a number of active and passive modules described in this paper including high voltage and high-power devices, complementary PNPs, high quality MIM capacitors, and inductors. Key RF circuit results highlighting the advantages of SiGe BiCMOS in addressing today's RF IC market are also discussed both for applications at modest frequencies (1 to 10 GHz) as well as for emerging applications at higher frequencies (20 to >100 GHz).     

Self-Aligned Wafer-Level Integration Technology With High-Density Interconnects and Embedded Passives

This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 mum are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-mum CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved     

光有源器件中的光集成技术演变

从光集成技术在光有源器件中的应用与发展的角度出发,结合硅光平台、平面光回路、光子集成回路以及光电子集成回路等基本的光集成技术平台,分析了光有源器件中的光集成技术的演变趋势,并给出了对未来光集成技术发展的展望。     

Multiband cellular RF solutions

This paper presents the integration trends and technology options for a multiband cellular RF solution. On the product level, forward integration evolves from the PA function via a transmit front-end to a fully integrated radio. On the component level, the main challenge is in the passives and the dedicated technologies developed for this.