The single burst error detection performance of binary cyclic codes

Using a new statistical model for burst errors, the authors calculate the conditional probability of undetected error for CRC codes with generator polynomials of the form g(x)=(1+x)p(x), p(x) a primitive polynomial. They show that the choice of p(x) affects the performance of these codes     

A Comparison of Some Error Detecting CRC Code Standards

Many data communication systems make use of cyclic redundancy check (CRC) codes for error detection purposes. In this paper, an asymptotic result concerning the undetected error probabilityP(epsilon)of CRC codes is derived. TheP(epsilon)'s of a number of CRC codes which have been adopted as international standards are also examined.     

Fast Error Decoding with Binary VLSI Logic

Maximal distance binary codes that are composed of individual characters from the residues of pairwise prime polynomials are constructed and compared to Reed-Solomon codes. Although these binary residue codes are not as efficient as R-S codes in that codeword lengths are shorter, error decoding involves only binary and not finite field operations and thus allows faster decoding and greater data rates. Data rates of hundreds of megabits per second are feasible if decoding is implemented with VLSI array logic. Constructions of array logic for use in decoding are described. These codes lend themselves for use in a concatenated coding scheme.     

Some two-weight codes with composite parity-check polynomials (Corresp.)

The Hamming weight enumerator polynomials of some two-weight codes are presented. The codes have parity-check polynomials which are products of two irreducible polynomials.     

基于FPGA的CRC编码器的实现

在数据通信中为了降低通信线路传输的误码率,需要采用高效能的差错控制方法,循环冗余校验CRC（Cyclic Redundancy Check）由于编码简单且有效,是一种最常用的信道编码方法.介绍了CRC编码的原理算法和校验规则,以CRC-4为例,给出了CRC校验码的具体计算过程和使用硬件描述语言VHDL来实现CRC编码的流程图,在程序中实现的是串行移位计算,并以Altera公司开发的EDA工具QuartusⅡ作为编译、仿真平台,选用Cyclone系列中的EP1C6T144C6器件,完成了CRC编码器的FPGA实现,其实现速度可达397 MHz.     

Huffman code based error screening and channel code optimization for error concealment in perceptual audio coding (PAC) algorithms

The class of perceptual audio coding (PAC) algorithms yields efficient and high-quality stereo digital audio bitstreams at bit rates from 16 kb/sec to 128 kb/sec (and higher). To avoid "pops and clicks" in the decoded audio signals, channel error detection combined with source error concealment, or source error mitigation, techniques are preferred to pure channel error correction. One method of channel error detection is to use a high-rate block code, for example, a cyclic redundancy check (CRC) code. Several joint source-channel coding issues arise in this framework because PAC contains a fixed-to-variable source coding component in the form of Huffman codes, so that the output audio packets are of varying length. We explore two such issues. First, we develop methods for screening for undetected channel errors in the audio decoder by looking for inconsistencies between the number of bits decoded by the Huffman decoder and the number of bits in the packet as specified by control information in the bitstream. We evaluate this scheme by means of simulations of Bernoulli sources and real audio data encoded by PAC. Considerable reduction in undetected errors is obtained. Second, we consider several configurations for the channel error detection codes, in particular CRC codes. The preferred set of formats employs variable-block length, variable-rate outer codes matched to the individual audio packets, with one or more codewords used per audio packet. To maintain a constant bit rate into the channel, PAC and CRC encoding must be performed jointly, e.g., by incorporating the CRC into the bit allocation loop in the audio coder.     

在CRC校验中提高码率的新方法

本文提出了扩展缩短码的新概念 ,研究了线性和非线性扩展缩短码的构造方法 ,对线性和非线性扩展缩短码的性能进行了理论分析 ,并通过 C+ +和 MATLAB相结合的仿真方法 ,分析了扩展缩短码的最小距离、码重分布、不可检错误概率等方面的性能 ,比较了扩展缩短码和原缩短码以及冗余分配方式不同的两种非线性扩展缩短码性能的优劣。结果表明 :扩展缩短码的理论是原 CRC码理论的完善和补充。本研究为 GSM系统提出了一种新的选择方法。在某些要求码率较高但冗余度不变的通信设备中 ,扩展缩短码是较好的选择     

Weighted sum codes for error detection and their comparison withexisting codes

Describes a new family of error detection codes called weighted sum codes. These codes are preferred over four existing codes (CRC, Fletcher checksum, Internet checksum, and XTP CXOR), because they combine powerful error detection properties (as good as the CRC) with attractive implementation properties. One variant, WSC-1, has efficient software and hardware implementations; while a second variant, WSC-2, is almost as efficient in software (still significantly better than CRC) and offers commutative processing (that enables efficient out-of-order, parallel, and incremental update processing)     

新型级联Polar码设计

Polar码是一种新型高效的信道编码技术,被确定为5G增强移动宽带场景控制信道的编码方案。本文提出一种循环冗余校验(Cyclic Redundancy Check, CRC)码、奇偶校验(Parity Check, PC)码与Polar码级联方案,其中CRC码、PC码作为外码,Polar码作为内码。与CRC辅助的Polar码方案相比,新型级联Polar码在译码的过程中利用PC比特辅助路径度量值进行译码路径的修剪,用以保证路径选择的可靠性,从而提高了其纠错性能,由于PC操作简单,在复杂度上没有明显增加。仿真结果表明:新型级联Polar码具有优异的性能,当误码率为10-6,码长为512,码率为1/3时,新型级联Polar码与CRC辅助的Polar码相比大约有0.12 dB的增益。      

Optimal covering polynomial sets correcting three errors for binarycyclic codes

The covering polynomial method is a generalization of error-trapping decoding and is a simple and effective way to decode cyclic codes. For cyclic codes of rate R<2/τ, covering polynomials of a single term suffice to correct up to τ errors, and minimal sets of covering polynomials are known for various such codes. In this article, the case of τ=3 and of binary cyclic codes of rate R⩾2/3 is investigated. Specifically, a closed-form specification is given for minimal covering polynomial sets for codes of rate 2/3⩽R<11/15 for all sufficiently large code length n; the resulting number of covering polynomials is, if R=2/3+ρ with ρ>0, equal to nρ+2V√nρ+(1/2) log_φ(n/ρ)+O(1), where φ=(1+√5)/2. For all codes correcting up to three errors, the number of covering polynomials is at least nρ+2√nρ+O(log n); covering polynomial sets achieving this bound (and thus within O(log n) of the minimum) are presented in closed-form specifications for rates in the range 11/15⩽R<3/4     

Cross parity check convolutional codes

A class of convolutional codes called cross parity check (CPC) codes, which are useful for the protection of data stored on magnetic tape, is described and analyzed. CPC codes are first explained geometrically; their construction is described in terms of constraining data written onto a tape in such a way that when lines of varying slope are drawn across the tape, the bits falling on those lines sum to zero modulo two. This geometric interpretation is then formalized by the construction of canonical parity check matrices and systematic generator matrices for CPC codes and by computing their constraint lengths. The distance properties of CPC codes are analyzed, and it is shown that these codes are maximum distance separable convolutional codes. In addition, examples are given of both error and erasure decoding algorithms that take advantage of the geometric regularity of CPC codes. The technique of parity check matrix reduction, which is useful for reducing the inherent decoding delay of CPC codes, is described. The technique consists of dividing each term of the parity check matrix by some polynomial and retaining only the remainder. A class of polynomials that are particularly attractive for this purpose if identified     

On covering radii and coset weight distributions of extremal binaryself-dual codes of length 56

We present a method to determine the complete coset weight distributions of doubly even binary self-dual extremal [56, 28, 12] codes. The most important steps are (1) to describe the shape of the basis for the linear space of rigid Jacobi polynomials associated with such codes in each index i, (2) to describe the basis polynomials for the coset weight enumerators of the assigned coset weight i by means of rigid Jacobi polynomials of index i. The multiplicity of the cosets of weight i have a connection with the frequency of the rigid reference binary vectors v of weight i for the Jacobi polynomials. This information is sufficient to determine the complete coset weight distributions. Determination of the covering radius of the codes is an immediate consequence of this method. One important practical advantage of this method is that it is enough to get information on 8190 codewords of weight 12 (minimal-weight words) in each such code for computing every necessary information     

Fast software implementation of error detection codes

Software implementations of error detection codes are considered to be slow compared to other parts of the communication system. This is especially true for powerful error detection codes such as CRC. However, we have found that powerful error detection codes can run surprisingly fast in software. We discuss techniques for, and measure the performance of, fast software implementation of the cyclic redundancy check (CRC), weighted sum codes (WSC), one's-complement checksum, Fletcher (1982) checksum, CXOR checksum, and block parity code. Instruction count alone does not determine the fastest error detection code. Our results show the computer memory hierarchy also affects performance. Although our experiments were performed on a Sun SPARCstation LX, many of the techniques and conclusions will apply to other processors and error detection codes. Given the performance of various error detection codes, a protocol designer can choose a code with the desired speed and error detection power that is appropriate for his network and application     

Error-burst detection with tandem CRCs

The authors investigate the efficacy of using two different cyclic redundancy check (CRC) codes in tandem to increase error-burst detecting capability. For a set of pairs of CRCs which are used in standards, it is found that the guaranteed detectable burst length is less than the sum of the individual guaranteed detectable burst lengths, but not much less. Thus strengthened CRC codes can readily be obtained using existing devices     

Designing fault-secure parallel encoders for systematic linear error correcting codes

We consider the open problem of designing fault-secure parallel encoders for various systematic linear ECC. The main idea relies on generating not only the check bits for error correction but also, separately and in parallel, the check bits for error detection. Then, the latter are compared against error detecting check bits which are regenerated from the error correcting check bits. The detailed design is presented for encoders for CRC codes. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that their fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation. Future research will include the design of FS decoders for CRC codes as well as the generalization of the presented ideas to design of FS encoders and decoders for other systematic linear ECC like nonbinary BCH codes and Reed-Solomon codes.     

New convolutional code constructions and a class of asymptotically good time-varying codes

We show that the generator polynomials of certain cyclic codes define noncatastrophic fixed convolutional codes whose free distances are lowerbounded by the minimum distances of the cyclic codes. This result is used to construct convolutioual codes with free distance equal to the constraint length and to derive convolutional codes with good free distances from the BCH codes. Finally, a class of time-varying codes is constructed for which the free distance increases linearly with the constraint length.     

A simple method to determine the number of true different quadratic and cubic permutation polynomial based interleavers for turbo codes

Interleavers are important blocks of the turbo codes, their types and dimensions having a significant influence on the performances of the mentioned codes. If appropriately chosen, the permutation polynomial (PP) based interleavers lead to remarkable performances of these codes. The most used interleavers from this category are quadratic permutation polynomial (QPP) and cubic permutation polynomial (CPP) based ones. In this paper, we determine the number of different QPPs and CPPs that cannot be reduced to linear permutation polynomials (LPPs) or to QPPs or LPPs, respectively. They are named true QPPs and true CPPs, respectively. Our analysis is based on the necessary and sufficient conditions for the coefficients of second and third degree polynomials to be QPPs and CPPs, respectively, and on the Chinese remainder theorem. This is of particular interest when we need to find QPP or CPP based interleavers for turbo codes.     

Optimum cyclic redundancy codes for noisy channels (Corresp.)

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16-bit ADCCPt polynomial is designed for digital links that already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of the resulting digital circuit may be much lower. This leads to the consideration of 3-byte (24-bit) and 4-byte (32-bit) polynomials. Generator polynomials of a certain class are found that have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular polynomials for 24-bit and 32-bit redundancies are exhibited, of weight and distance 6 in the 24-bit case and weight 10 and distance 8 in the 32-bit case.     

液晶电视中系统参数的检纠错备份机制及检验方法

在液晶电视的嵌入武系统中,系统参数通常存放在主板芯片E2 PROM里,由于外界脉冲或其TA原因会使E2 PROM中的数据发生丢失或错误,从而导致液晶电视偏色或无法正常启动.为解决此问题,提出一种利用CRC检错码和RS纠错码的机制来实现对系统参数的备份,即使数据发生部分错误也能够即时纠正过来.同时,为了检验基于检错和纠错数据备份机制的可靠性,设计了一套能够针对液晶电视主板上E2 PROM芯片中数据的正确性进行测试的工具,在一线工厂应用价值较高.     

High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

This brief presents a high-speed parallel cyclic redundancy check (CRC) implementation based on unfolding, pipelining, and retiming algorithms. CRC architectures are first pipelined to reduce the iteration bound by using novel look-ahead pipelining methods and then unfolded and retimed to design high-speed parallel circuits. A comparison on commonly used generator polynomials between the proposed design and previously proposed parallel CRC algorithms shows that the proposed design can increase the speed by up to 25% and control or even reduce hardware cost