Thin RF sputtered and thermal Ta2O5 on Si for high density DRAM application

Tantalum pentoxide thin films on Si prepared by two conventional for modern microelectronics methods (RF sputtering of Ta in Ar + O₂ mixture and thermal oxidation of tantalum layer on Si) have been investigated with respect to their dielectric, structural and electric properties. It has been found that the formation of ultra thin SiO₂ film at the interface with Si, during fabrication implementing the methods used, is unavoidable as both, X-ray photoelectron spectroscopy and electrical measurements, have indicated. The initial films (as-deposited and as-grown) are not perfect and contain suboxides of tantalum and silicon which act as electrical active centers in the form of oxide charges and interface states. Conditions which guarantee obtaining high quality tantalum oxide with dielectric constant of 32–37 and leakage current density less than 10⁻⁷ A/cm² at 1.5 V applied voltage (Ta₂O₅ thickness equivalent to about 3.5 nm of SiO₂) have been established. These specifications make the layers obtained suitable alternative to SiO₂ for high density DRAM application.     

Effect of microwave radiation on the properties of Ta2O5–Si microstructures

The paper presents results of the effect of microwave irradiation at room temperature on the properties of thin layers of tantalum pentoxide deposited on Si by rf sputtering. Electrical characterization is performed in conjunction with Auger electron spectroscopy and atomic force microscopy. Among exposure times used (1; 5; 10 s), treatment of about 5 s shows the best promise as an annealing step––an improvement of number of parameters of the system Ta₂O₅–Si is established (dielectric constant and surface morphology; stoichiometry and microstructure of both the bulk oxide and the interfacial transition region; electrical characteristics in terms of oxide charge density, leakage current and breakdown fields). At the same time the microwave irradiation is not accompanied by crystalization effects in Ta₂O₅ and/or additional oxidation of Si substrate. It is concluded that the short-time microwave irradiation can be used as an annealing process for Ta₂O₅–Si microstructures and it has a potential to replace the high-temperature annealing processes for high-k insulators.     

Breakdown fields and conduction mechanisms in thin Ta2O5 layers on Si for high density DRAMs

The conduction mechanisms and the microstructure of rf sputtered Ta₂O₅ on Si, before and after oxygen annealing at high temperatures (873, 1123 K; 30 min) have been investigated. The as-deposited and annealed at 873 K layers are amorphous whereas crystalline Ta₂O₅ (orthorhombic β-Ta₂O₅ phase) was obtained after O₂ treatment at 1123 K. The results (electrical, X-ray diffraction, transmission electron microscopy) reveal the formation of an interfacial ultrathin SiO₂ layer under all technological regimes used. The higher (493 K) substrate temperature during deposition stimulates the formation of amorphous rather than crystalline SiO₂. It is found that the oxygen heating significantly reduces the oxide charge (Q_f<10¹⁰ cm⁻²) and improves the breakdown characteristics (the effect is more pronounced for the higher annealing temperature). It is accompanied by an increase of the effective dielectric constant (up to 37 after 1123 K treatment). It is established that the influence of the oxygen treatment on the leakage current is different depending on the film thickness, namely: a beneficial effect for the thinner and a deterioration of leakage characteristics for thicker (80 nm) films. A leakage current density as low as 10⁻⁷ A/cm² at 1 MV/cm applied field for 26 nm annealed layers has been obtained. The current reduction is considered to be due to a removal by annealing of certain structural nonperfections present in the initial layers. Generally, the results are discussed in terms of simultaneous action of two opposite and competing processes taking place at high temperatures––a real annealing of defects and an appearance of a crystal phase and/or a neutral traps generation. The contribution of the neutral traps also is involved to explain the observed weaker charge trapping in the as-fabricated films compared to the annealed ones.The conduction mechanism of the as-deposited films is found to be of Poole–Frenkel (PF) type for a wide range of applied fields. A change of the conduction mechanism for the annealed films at medium fields (0.8–1.3 MV/cm) is established. This transition from PF process to the Schottky emission limited current is explained with an annealing of bulk traps (oxygen vacancies and nonperfect bonds). It is concluded that the dominant conduction mechanism in the intermediate fields can be effectively controlled by appropriate technological steps.     

Transients during pre-breakdown and hard breakdown of thin gate oxides in metal–SiO2–Si capacitors

Time–resolved electrical measurements show transient phenomena occurring during degradation and intrinsic dielectric breakdown of gate oxide layers under constant voltage Fowler–Nordheim stress. We have studied such transients in metal/oxide/semiconductor (MOS) capacitors with an n⁺ poly-crystalline Si/SiO₂/n-type Si stack and with oxide thickness between 35 and 5.6 nm. The data adds new information concerning the intrinsic breakdown mechanism and these are shown and discussed together with the adopted measurement techniques.     

Examination and evaluation of La2O3 as gate dielectric for sub-100 nm CMOS and DRAM technology

High-k gate dielectric La₂O₃ thin films have been deposited on Si(1 0 0) substrates by molecular beam epitaxy (MBE). Al/La₂O₃/Si metal-oxide–semiconductor capacitor structures were fabricated and measured. A leakage current of 3 × 10⁻⁹ A/cm² and dielectric constant between 20 and 25 has been measured for samples having an equivalent oxide thickness (EOT) 2.2 nm. The estimated interface state density D_it is around 1 × 10¹¹ eV⁻¹ cm⁻². EOT and flat-band voltage were calculated using the NCSU CVC program. The chemical composition of the La₂O₃ films was measured using X-ray photoelectron spectrometry and Rutherford backscattering. Current density vs. voltage curves show that the La₂O₃ films have a leakage current several orders of magnitude lower than SiO₂ at the same EOT. Thin La₂O₃ layers survive anneals of up to 900 °C for 30 s with no degradation in electrical properties.     

Influence of oxidation temperature on the microstructure and electrical properties of Ta2O5 on Si

The effect of the oxidation temperature (673-873 K) on the microstructural and electrical properties of thermal Ta₂O₅ thin films on Si has been studied. Auger electron spectroscopy and X-ray photoelectron spectroscopy results revealed that the films are non-stoichiometric in the depth; an interfacial transition layer between tantalum oxide and Si substrate, containing presumably SiO₂ was detected. It has been found by X-ray diffraction that the amorphous state of Ta₂O₅ depends on both the oxidation temperature and the thickness of the films—the combination of high oxidation temperature (>823 K) and thickness smaller than 50 nm is critical for the appearance of a crystal phase. The Ta₂O₅ layers crystallize to the monoclinic phase and the temperature of the phase transition is between 773 and 823 K for the thinner layers (<50 nm) and very close to 873 K for the thicker ones. The electrical characterization (current/voltage; capacitance/voltage) reveals that the optimal oxidation temperature for achieving the highest dielectric constant (∼32) and the lowest leakage current (10⁻⁸ A/cm² at 1 MV/cm applied field) is 873 K. The results imply that the poor oxidation related defects are rather the dominant factor in the leakage current than the crystallization effects.     

Electrical instability of sintered Ta films on (vacuum evaporated) polysilicon structures

High purity tantalum metal was deposited on finely polished single crystal, polycrystalline silicon substrates and on the thermally grown oxide layers as a combination of Si/SiO₂/poly-Si/Ta, under oil-free ultra-high vacuum conditions, of the order of 6.0 × 10⁻⁹ Torr, at a deposition rate of 2.0 Å s⁻¹, using an e-beam evaporator. The measured resistivity of the as-deposited tantalum films show relatively high resistivity values to that of the bulk. Thermal annealing of these poly-Si/Ta, under argon (with 10% H₂) ambient, shows the increase in the resistivity values at relatively low temperatures, and it was observed that the film's electrical conductivity ceases in the temperature range of 500–600°C. The oxidation properties of tantalum and the possible formation of TaSi₂ and Ta₂O₅ were analysed for from a reliability point of view.     

A new MOD method to prepare Sr0.7Bi2.2Ta2O9 ferroelectric films for non-volatile RAM memories

Strontium bismuth tantalate, Sr_0.7Bi_2.2Ta₂O₉ (SBT), thin films were prepared by a new metalorganic decomposition (MOD) method using strontium (2,2,6,6-tetramethyl-3,5-heptanedionate), bismuth (2,2,6,6-tetramethyl-3,5-heptanedionate), and tantalum ethoxide as the metalorganic precursors. Films with a thickness of 300 nm were prepared on Si(1 0 0) with a layered bottom electrode (Pt/TiO₂/SiO₂). After crystallization in oxygen for 60 min at 750°C, single orthorhombic-phased films were obtained as determined by XRD, but no preferred crystalline orientation was revealed using this technique. Characterization by AFM showed that the polycrystalline films were densely packed and crack-free, and had an average surface roughness (rms) of 8 nm and a mean grain size of 150 nm. The remnant polarization and coercive field were 6 μC cm⁻² and 74 kV cm⁻¹, respectively. The SBT films showed a very low polarization fatigue after 10¹¹ switching cycles and good retention properties.     

Characteristics of MIS capacitors based on multilayer TiO2–Ta2O5 structures

We report electrical characteristics of multilayer TiO₂–T₂O₅ based MIS structures obtained by simple electron beam evaporation and annealed in an O₂ environment. We describe parameter dependence on annealing conditions and demonstrate an equivalent SiO₂ thickness of 3 nm with a leakage current density of 10⁻⁷ A/cm² at an electric field of 10⁶ V/cm.     

Carrier mobility in inversion layers of Si–thin Ta2O5 structures

The behaviour of carrier mobility in the inversion channel of gateless p-MOSFETs with thin (7-50 nm) Ta₂O₅ layers, having a dielectric constant of (23-27) and prepared by rf sputtering of Ta in an Ar-O₂ mixture, has been investigated. It is shown that independently of the high dielectric constant of the layers, the transport properties in the channel are strongly affected by defects in Ta₂O₅/Si system in the form of oxide charge and interface states. These defects act as scattering centers and are responsible for the observed minority carrier mobility degradation. Both, the oxide and the interface state charges are virtually independent on the oxygen content (in the range 10-30%) during the sputtering process. A reduction of the oxide charge and the density of interface states with increasing Ta₂O₅ film thickness was found, which results in the observed increase of the inversion channel mobility with thickness. It is assumed that the bond defects (broken or strained Ta-bonds as well as weak Si-O bonds in the transition region between Ta₂O₅ and Si) are much more probable sources of defect centers rather than Ta and O vacancies or impurities.     

Comparison between the properties of amorphous and crystalline Ta2O5 thin films deposited on Si

In this study, the structural and electrical properties of amorphous and crystalline Ta₂O₅ thin films deposited on p-type Si by low pressure metalorganic chemical vapour deposition from a Ta(OC₂H₅)₅ source have been investigated. The as-deposited layers are amorphous, whereas crystalline Ta₂O₅ (hexagonal phase) was obtained after post-deposition O₂-annealing at 800°C. Physico-chemical analysis of our layers shows that the O₂-treatment leads to the growth of a thin (1 nm) interfacial SiO₂ layer between Ta₂O₅ and Si but, contrary to other studies, was not sufficient to reduce the level of carbon and hydrogen contaminants. Crystalline Ta₂O₅ shows better leakage current properties than amorphous Ta₂O₅. The conduction mechanism in amorphous Ta₂O₅ is clearly attributed to the Poole–Frenkel effect with a barrier height separating the traps from the conduction band of 0.8 eV. For crystalline Ta₂O₅, the situation remains unclear since no simple law can be invoked due to the presence of the SiO₂ interlayer: a double conduction process based on a tunnelling effect in SiO₂ followed by a trap-modulated mechanism in Ta₂O₅ may be invoked. From capacitance–voltage measurements, the permittivity was found to be 25 for amorphous samples, but values ranging from 56 to 59 were found for crystalline layers, suggesting a high anisotropic character.     

Electrical properties of thin Ta2O5 films obtained by thermal oxidation of Ta on Si

Tantalum pentoxide films (13–260 nm) on p-type Si have been prepared by thermal oxidation at 673–873 K of rf sputtered Ta films and have been studied using Al–Ta₂O₅–Si capacitors. Both dielectric constant and refractive index were found to depend on the thickness of the Ta₂O₅ layers. Layers with a dielectric constant of 25–32 were obtained. A decreasing trend in the leakage current was found upon increasing oxidation temperature from 673 to 873 K. Leakage current density of (10⁻⁸ to 3×10⁻⁷) A cm⁻² at 1 MV cm⁻¹ effective field was achieved.     

High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity

Electrical properties of mixed HfO₂-Ta₂O₅ films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO₂ addition to the Ta₂O₅ is thickness dependent and the thicker layers exhibit advantages over the pure Ta₂O₅ (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO₂ and Ta₂O₅ mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta₂O₅-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO₂-Ta₂O₅ stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.     

Bulk oxide charge and slow states in Si–SiO2 structures generated by RIE-mode plasma

The damage induced in the thin SiO₂–Si system after an exposure to O₂ and N₂ plasma working in reactive ion etching (RIE) mode has been studied. A generation of high density (up to 5×10¹² cm⁻² in the first 15 s plasma exposure) of positive oxide charge in bulk traps as well as in slow states has been established. The RIE damage effects become highly process dependent as the plasma time increases, the fixed oxide charge first increases and then slows down or even turns around depending on discharge conditions. It is suggested that the relative contribution of the two main plasma components (ion bombardment and vacuum UV photons) at different discharge regimes is the reason for the appearance or the absence of the “turn-around” effect. It is established that the combination O₂ plasma and low pressure is critical for the degradation of the plasma treated samples. The results reveal a strong linear correlation between the leakage current detected and plasma created positive charge.     

Electrical characterisation of Si3N4/SiO2 double layers on p-type 6H–SiC

MNOS, MNS and MOS devices have been fabricated on p-type 6H–SiC substrates without epitaxial layers. They have been characterised using high frequency CV, GV, and IV measurements. The high frequency CV characteristics of p-type 6H–SiC MNOS structures indicate a very similar interface quality to p-type 6H–SiC MOS devices. A lower effective fixed insulator charge Q_I is found in MNOS devices with a higher oxide thickness x_ox. An x_ox of 10 nm is effective in avoiding charge instability. The effective fixed insulator charge Q_I can be modified in the 10 nm oxide SiC MNOS devices by injecting carriers into the nitride. Similar leakage current characteristics compared to p-type 6H–SiC MNS structures have been found for p-type 6H–SiC MNOS devices, but the SiO₂/Si₃N₄ insulator current is lower, particularly for positive electric fields. At the oxide breakdown limit (−10 MV/cm), Poole–Frenkel conduction is observed in the nitride for negative electric fields due to direct tunnelling of holes into the nitride.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Optical and electrical characterization of the electron beam gun evaporated TiO2 film

We report measured evolutions of the optical band gap, refractive index and relative dielectric constant of TiO₂ films obtained by electron beam gun evaporation and annealed in an oxygen environment. A negative shift of the flat band voltage with increasing annealing temperatures, for any film thickness, is observed. A dramatic reduction of the leakage current by about four orders of magnitude to 5×10⁻⁶ A cm⁻² (at 1 MV cm⁻¹) after 700°C and 60 min annealing is found for films thinner than 15 nm. The basic carrier transport mechanisms at different ranges of applied voltage such as hopping, space charge limited current and Fowler–Nordheim is established. An equivalent SiO₂ thickness in order of 3.5 nm is demonstrated.     

Correlation between infrared transmission spectra and the interface trap density of SiO2 films

This work is an attempt to estimate the electrical properties of SiO₂ thin films by recording and analyzing their infrared transmission spectra. In order to study a big variety of films having different infrared and electrical properties, we studied SiO₂ films prepared by low pressure chemical vapor deposition (LPCVD) from SiH₄ + O₂ mixtures at 425 °C and annealed at 750 °C and 950 °C for 30 min. In addition thermally grown gate quality SiO₂ films of similar thickness were studied in order to compare their infrared and electrical properties with the LPCVD oxides. It was found that all studied SiO₂ films have two groups of Si–O–Si bridges. The first group corresponds to bridges located in the bulk of the film and far away from the interfaces, the grain boundaries and defects and the second group corresponds to all other bridges located near the interfaces, the grain boundaries and defects. The relative population of the bulk over the boundary bridges was found equal to 0.60 for the LPCVD film after deposition and increased to 4.0 for the LPCVD films after annealing at 950 °C. Thermally grown SiO₂ films at 950 °C were found to have a relative population of Si–O–Si bridges equal to 3.9. The interface trap density of the LPCVD film after deposition was found equal to 5.47 × 10¹² eV⁻¹ cm⁻² and decreases to 6.50 × 10¹⁰ eV⁻¹ cm⁻² after annealing at 950 °C for 30 min. The interface trap density of the thermally grown film was found equal to 1.27 × 10¹¹ eV⁻¹ cm⁻² showing that films with similar Si–O–Si bridge populations calculated from the FTIR analysis have similar interface trap densities.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Investigation of Ta2O5/SiO2/4H-SiC MIS capacitors

Tantalum pentoxide (Ta₂O₅) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta₂O₅ of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta₂O₅. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta₂O₅ and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta₂O₅ at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta₂O₅/SiO₂/4H-SiC capacitors.