A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers

A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in an RF Si-bipolar process with an f/sub T/ of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP/sub 3/ (+15.5-dBm OIP/sub 3/) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA DC current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with -10 to -41-dB S/sub 11/ is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 /spl times/ 0.9 mm/sup 2/. The circuit is suitable for area-efficient multiband multistandard low-IF receivers.     

Monolithic integrated blanking up-converter

A novel GaAs monolithic integrated DC-coupled up-converter is presented. It up-converts a 0.1- to 0.5-GHz signal to 0.6 to 1.75 GHz. The high level of integration has been achieved in a small chip size of 1.22 mm×1.22 mm by utilizing active matching techniques. A wideband local oscillator (LO) amplifier, an active 180° splitter, a double-balanced mixer, an RF amplifier, an actively matched IF amplifier, and an RF blanking circuit are integrated on a GaAs chip. The up-converter exhibits an 8-dB conversion gain, a maximum input/output voltage standing wave ratio (VSWR) of less than 1.6, and a 40-dB RF blanking for an IF of 0.1 to 0.5 GHz and LO of 0.5-1.25 GHz. The measured results are in good agreement with the simulated results     

A high-performance W-band uniplanar subharmonic mixer

A uniplanar subharmonic mixer has been implemented in coplanar waveguide (CPW) technology. The circuit is designed to operate at RF frequencies of 92-96 GHz, IF frequencies of 2-4 GHz, and LO frequencies of 45-46 GHz. Total circuit size excluding probe pads and transitions is less than 0.8 mm ×1.5 mm. The measured minimum single-sideband (SSB) conversion loss is 7.0 dB at an RF of 94 GHz, and represents state-of-the-art performance for a planar W-band subharmonic mixer. The mixer is broad-band with a SSB conversion loss of less than 10 dB over the 83-97-GHz measurement band. The measured LO-RF isolation is better than -40 dB for LO frequencies of 45-46 GHz. The double-sideband (DSB) noise temperature measured using the Y-factor method is 725 K at an LO frequency of 45.5 GHz and an IF frequency of 1.4 GHz. The measured data agrees well with the predicted performance using harmonic-balance analysis (HBA). Potential applications are millimeter-wave receivers for smart munition seekers and automotive-collision-avoidance radars     

Integrated balanced sampling circuit for ultra-wideband communications and radar systems

A balanced sampling circuit realized using step recovery and Schottky diodes on coplanar waveguide, coplanar strips, and slotlines is presented for ultra-wideband communications and radar applications. An efficient design was implemented to achieve improved performance. The impulse generator, providing signal for the sampling gate, was designed with a new LO feeding structure. The fabricated circuit shows 16-19 dB conversion loss without amplifier and 1-4 dB conversion gain with amplifier across 9-GHz RF bandwidth with 500-MHz sampling frequency.     

A 1.9-GHz silicon receiver with monolithic image filtering

A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (f_T). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz     

一款集成驱动放大器的低变频损耗混频器设计

采用0.5μm GaAs工艺设计并制造了一款单片集成驱动放大器的低变频损耗混频器.电路主要包括混频部分、巴伦和驱动放大器3个模块.混频器的射频(RF)、本振(LO)频率为4～7 GHz,中频(IF)带宽为DC～2.5 GHz,芯片变频损耗小于7 dB,本振到射频隔离度大于35 dB,本振到中频隔离度大于27 dB.1 dB压缩点输入功率大于11 dBm,输入三阶交调点大于20 dBm.该混频器单片集成一款驱动放大器,解决了无源混频器要求大本振功率的问题,变频功能由串联二极管环实现,巴伦采用螺旋式结构,在实现超低变频损耗和良好隔离度的同时,保持了较小的芯片面积.整体芯片面积为1.1 mm×1.2 mm.     

12-GHz-Band GaAs Dual-Gate MESFET Monolithic Mixers

12-GHz-band GaAs dual-gate MESFET monolithic mixers have been developed for use in direct broadcasting satellite receivers. In order to reduce chip size, a buffer amplifier has been connected directly after a mixer IF port, instead of employing an IF matching circuit. The mixer and the buffer were fabricated on separate chips, so that individual measurements could be achieved. Chip size is 0.96X 1.26 mm for the mixer and 0.96X0.60 mm for the buffer. A dual-gate FET for the mixer, as well as a single-gate FET for the buffer, has a closely spaced electrode structure. Gate length and width are 1 µm and 320 µm, respectively. The mixer with the buffer provides 2.9+-0.4-dB conversion gain with 12.3+-0.3dB SSB noise figure in the 11.7-12.2-GHz RF band. Local oscillator (LO) frequency is 10.8 GHz. A low-noise converter was constructed by connecting a monolithic preamplifier, an image rejection filter, and a monolithic IF amplifier to the mixer. The converter provides 46.8+-1.5-dB conversion gain with 2.8+-0.2-dB SSB noise figure in the same frequency band.     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

A subharmonic self-oscillating mixer with integrated antenna for60-GHz wireless applications

A balanced integrated-antenna self-oscillating mixer at 60 GHz is presented in this paper. The modal radiation characteristics of a dual-feed planar quasi-Yagi antenna are used to achieve RF-local oscillator (RF-LO) isolation between closely spaced frequencies. The balanced mixer is symmetric, inherently broad band, and does not need an RF balun. Pseudomorphic high electron-mobility transistors are used in a 30-GHz push-pull circuit to generate the second harmonic and a 30-GHz dielectric resonator was used to stabilize the fundamental oscillation frequency. This allows the possibility of building a balanced low-cost self-contained antenna integrated receiver with low LO leakage for short-range narrow-band communication. Phase locking can be done with half of the RF frequency. The circuit exhibits a conversion loss less than 15 dB from 60 to 61.5 GHz, radiation leakage of -26 dBm at 60 GHz, and IF phase noise of -95 dBc/Hz at 100-kHz offset     

A 26-GHz Band Integrated Circuit of a Double-Balanced Mixer and Circulators

Integration of a double-balanced mixer and ferrite-disk type circulators have been successfully achieved in the 26-GHz band. The total single-sideband noise figure of the integrated circuit, composed of a mixer and two circulators, is 8.5 dB, including the noise contribution from an IF amplifier. The double-balanced mixer is composed of microstrip lines, slot lines, coupled slot lines, coplanar lines, Au wires, and four beam lead Schottky-barrier diodes. The minimum conversion loss of the mixer is 5.3 dB at a signal frequency of 25.4 GHz. Isolation between RF and LO ports is greater than 30 dB. The ferrite-disk type circulator is produced by a newly developed precise machining technique. The minimum insertion loss of the circulator is 0.45 dB, and the isolation is greater than 20 dB. The integrated circuit with the ferrite-disk type circulators will be extended to the millimeter-wave band.     

宽带高增益输出平衡CMOS低噪声放大器的设计

设计了一种带片内变压器、适用于0.05～2.5 GHz频段的宽带低噪声放大器(LNA).电路设计采用了并行的共栅共源放大结构,将从天线接收到的单端输入信号转换为一对差分信号输出给后级链路.针对变压器结构的LNA噪声系数不够低和输出不平衡的问题,采用了缩放技术、噪声消除技术以及两级的全差分放大器作为输出缓冲级,来有效降低电路的噪声系数,提高增益和输出平衡度.电路采用TSMC 0.18μm 1P6M RF CMOS工艺设计仿真和流片,测试结果表明:在0.05 ～ 2.5 GHz频带范围内,该LNA的最高功率增益达24.5 dB,全频段内噪声系数为2.6～4 dB,输入反射系数小于-10 dB,输出差分信号幅度和相位差分别低于0.6dB和1.8°.     

GaAs Monolithic MIC's for Direct Broadcast Satellite Receivers

A 12-GHz low-noise amplifier (LNA), a 1-GHz IF amplifier (IFA), and an 11-GHz dielectric resonator oscillator (DRO) have been developed for DBS home receiver applications by using GaAs monolithic microwave integrated circuit (MMIC) technology. Each MMIC chip contains FET's as active elements and self-biasing source resistors and bypass capacitors for a single power supply operation. It also contairns dc-block and RF-bypass capacitors. The three-stage LNA exhibits a 3.4-dB noise figure and a 19.5-dB gain over 11.7-12.2 GHz. The negative-feedback-type three-stage IFA shows a 3.9-dB noise figure and a 23-dB gain over 0.5-1.5 GHz. The DRO gives 10.mW output power at 10.67 GHz, with a frequency stability of 1.5 MHz over a temperature range from -40-80°C. A direct broadcast satellite (DBS) receiver incorporating these MMIC's exhibits an overafl noise figure of /spl les/ 4.0 dB for frequencies from 11.7-12.2 GHz.     

A 23.8-GHz SOI CMOS tuned amplifier

A 23.8-GHz tuned amplifier is demonstrated in a partially scaled 0.1-μm silicon-on-insulator CMOS technology. The fully integrated three-stage amplifier employs a common-gate, source-follower, and cascode with on-chip spiral inductors and MOS capacitors. The gain is 7.3 dB, while input and output reflection coefficients are -45 and -9.4 dB, respectively. Positive gain is exhibited beyond 26 GHz. The amplifier draws 53 mA from a 1.5-V supply. The measured on-wafer noise figure is 10 dB, while the input-referred third-order intercept point is -7.8 dBm. The results demonstrate that 0.1-μm CMOS technology may be used for 20-GHz RF applications and suggest even higher operating frequencies and better performance for further scaled technologies     

一种高线性无源双平衡混频器

设计了一种适用于1.0～2.0 GHz的高线性下变频混频器。电路设计采用了无源双平衡结构,片内集成宽带巴伦、限幅本振放大器、混频核和偏置电路。为了提高混频器的线性度,在对无源双平衡的结构进行分析的基础上,折中选择混频核的晶体管尺寸,并优化了本振放大器输出信号的幅值及上升时间。基于0.35μm BiCMOS工艺进行了设计仿真,芯片面积为0.9 mm×1.8 mm。流片测试结果表明:射频频率1.0～2.0 GHz,对应本振频率1.0～2.0 GHz,最佳本振输入功率为0 dBm,转换增益大于-7.0 dB,射频输入三阶交调大于25 dBm,混频器工作电压为3.3 V,功耗为112 mW。该高线性无源双平衡混频器可满足工程应用。     

A 20 GHz microwave sampler

A microwave sampler circuit which operates over the frequency band of 1-20 GHz and has a number of novel features is described. These features include a wideband microstrip-to-slot balun and a wideband active isolator the function of which is to reduce the local oscillator to RF leakage from the input port of the sampler. The signal-to-noise ratio over the input bandwidth is greater than 20 dB at an input power level of -32 dBm. This signal-to-noise ratio was measured in an IF bandwidth of 175 MHz and includes the contribution from the IF amplifier. The sampler, which is made on alumina using MIC techniques, has an integrated impulse generator driven with a sinusoidal local oscillator of only 20 dBm over the frequency band of 250-350 MHz. The IF signal is in the 10-175-MHz band. The RF input VSWR is better than 2:1 up to 20 GHz, and the oscillator to RF breakthrough is better than -58 dBm (-78 dBc) when driven with a local oscillator of 20 dBm. This unusually low leakage was achieved by using the active isolator prior to the sampling circuit     

35-nm InP HEMT SMMIC Amplifier With 4.4-dB Gain at 308 GHz

rdquoWe report the first submillimeter-wave monolithic microwave integrated circuit (MMIC) amplifier with 4.4-dB measured gain at 308-GHz frequency, making it the highest frequency MMIC amplifier reported to date. In this letter, a 35-nm InP high-electron mobility transistor process has been successfully developed with a projected maximum available gain of greater than 7 dB at 300 GHz. The excellent dc and RF performance makes it suitable for applications at frequencies well into the millimeter-wave band and, for the first time, in the submillimeter- wave band as well.     

高幅相一致6—18 GHz下变频器设计

在射频超外差接收机中,下变频器是一种常用的功能组件,主要用于射频信号的侦测接收。针对6-18 GHz 频段,提出一种下变频器的设计方案。下变频器采用混合集成电路工艺,中频处理带宽1 GHz,噪声系数优于6 dB,幅度一致性优于±2 dB,相位一致性优于±15°,无虚假动态范围大于50 dB。组件内部采用多功能芯片和MEMS滤波器组,内置多级数控衰减和数控移相器。下变频器具有频段宽、体积小、集成度高、易于调试的优点。     

A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters

A wideband software-defined digital-RF modulator targeting Gb/s data rates is presented. The modulator consists of a 2.625-GS/s digital DeltaSigma modulator, a 5.25-GHz direct digital-RF converter, and a fourth-order auto-tuned passive LC RF bandpass filter. The architecture removes high dynamic range analog circuits from the baseband signal path, replacing them with high-speed digital circuits to take advantage of digital CMOS scaling. The integration of the digital-RF converter with an RF bandpass reconstruction filter eliminates spurious signals and noise associated with direct digital-RF conversion. An efficient passgate adder circuit lowers the power consumption of the high-speed digital processing and a quadrature digital-IF approach is employed to reduce LO feedthrough and image spurs. The digital-RF modulator is software programmable to support variable bandwidths, adaptive modulation schemes, and multi-channel operation within a frequency band. A prototype IC built in 0.13-mum CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. In-band LO and image spurs are less than -59 dBc without requiring calibration. The modulator consumes 187 mW and occupies a die area of 0.72 mm².     

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements     

A low-current Ku-band GaAs monolithic image rejectiondown-converter

A single-chip image rejection downconverter has been designed, fabricated. and tested for broadcast satellite receivers operating in the 11.7- to 12.2-GHz range. The downconverter consists of an RF low-noise amplifier (LNA), a filter-type image rejection mixer (IRM), and an intermediate frequency amplifier (IFA). It receives 11.7- to 12.2-GHz RF signals and down converts to 1.0- to 1.5-GHz IF signals with an external local oscillator. Since the filter integrated on the downconverter produces an image rejection of more than 30 dB, the downconverter requires no off-chip circuits for the image rejection. A conversion gain of 37±1 dB and a noise figure of less than 3.5 dB have been achieved over the RF frequency range. The current dissipation is only 40 mA, and the chip size is 2.8 mm×2.8 mm×0.45 mm