Computation of sensitivities of IC interconnect parasitic capacitances to the process variation with dual discrete geometric methods

Sensitivity analysis methods help to deal with the challenges of process variation in extraction of parasitic capacitances in an integrated circuit. The dual discrete geometric methods (DGMs), which have been recently utilized to extract parasitic capacitances, are reviewed. The computation method based on the dual DGMs for sensitivities of capacitances with respect to the given process parameters is presented. As the dual DGMs utilize scalar electric potential is unknown, the capacitances are obtained effectively, and then the sensitivities are calculated conveniently.     

一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

90 nm CMOS工艺下串扰延迟及其测量电路的研究

仿真分析了90 nm CMOS工艺中串扰延迟的趋势,结果表明,90 nm CMOS工艺下1 mm的连线延迟远大于单位门的延迟,最坏情况下1 mm连线延迟约为单位门延迟的6倍,而当线间耦合电容发生作用时,串扰延迟在连线延迟中起主要作用.提出了一种用于测量超深亚微米工艺串扰延迟的新型电路,电路主要由VCO和几个触发器组成,采用HSPICE对电路进行了仿真,结果表明所提出的电路最大测量误差为1.33%.     

CMOS驱动电路中信号延迟的精确计算

本文提出了树形网络ＣＭＯＳ驱动电路中信号延迟相对精确的计算表达式，它考虑了不同延迟定义下ＣＭＯＳ驱动电路等老头儿 导通电阻及负功电容的影响，可用于ＶＬＳＩ互连延迟的计算及时间驱动布图系统信号延迟计算中。     

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

A new two-dimensional C-V model for prediction of maximum frequency of oscillation (fmax) of deep submicron AlGaN/GaN HEMT for microwave and millimeter wave applications

An analytical two-dimensional capacitance-voltage model for AlGaN/GaN high electron mobility transistor (HEMTs) is developed, which is valid from a linear to saturation region. The gate source and gate drain capacitances are calculated for 120 nm gate length including the effects of fringing field capacitances. We obtain a cut-off frequency (f_T) of 120 GHz and maximum frequency of oscillations (f_max) of 160 GHz. The model is very useful for microwave circuit design and analysis. Additionally, these devices allow a high operating voltage V_DS, which is demonstrated in the present analysis. These results show an excellent agreement when compared with the experimental data.     

MOS Capacitance-Voltage Characteristics: V. Methods to Enhance the Trapping Capacitance

Low-frequency and High-frequency Capacitance-Voltage (C-V) curves of Silicon Metal-Oxide-linebreak Semiconductor Capacitors, showing electron and hole trapping at shallow-level dopant and deep-level generation-recombination-trapping impurities, are presented to illustrate the enhancement of the giant trapping capacitances by physical means via device and circuit designs, in contrast to chemical means via impurity characteristics previously reported. Enhancement is realized by masking the electron or/and hole storage capacitances to make the trapping capacitances dominant at the terminals. Device and materials properties used in the computed CV curves are selected to illustrate experimental realizations for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.     

采用轴对称二维有限元法提取过孔分布电容

采用简便的两维轴对称有限元法分析了四层印制电路板的过孔电容。将极坐标形式的拉普拉斯方程变换成直角坐标形式,避免了复杂的椭圆积分。将过孔的电容分层处理,分析了过孔的高度、半径、焊盘半径等参数对过孔电容的影响。与有限元分析软件ANSYS进行了对比,计算结果基本一致。此方法可用于任意层复杂印制电路板过孔电容的提取,所得结论有助于过孔的等效电路建模以及高速PCB的信号完整性分析。     

金丝球焊机金丝检测技术

在应用于三极管压焊的全自动金丝球焊机中,金丝检测是确保压焊过程工艺质量的关键技术。通过设计金丝的打火失球检测和第一焊点、第二焊点压焊失败检测电路,实现金丝球焊机的金丝压焊效果自动检测功能。实验证明,所设计的检测电路完全满足压焊工艺质量的要求。     

CCC Ⅱ模拟电感的非理想特性分析及应用

提出了利用理想第二代电流控制传输器(CCC II)模拟电感特性的结构。分析了基于CCC II模拟电感的理想电感效应有效范围、主要寄生电容电阻的影响及其补偿方法,给出了模拟电感特性仿真结果。在此基础上,对5阶巴特沃斯(Butterworth)高通滤波器进行综合。电路具有结构简单、集成度高,截止频率连续可调等优点。仿真结果证明了设计的正确性。     

MOS Capacitance-Voltage Characteristics:V.Methods to Enhance the Trapping Capacitance

正Low-frequency and High-frequency Capacitance-Voltage(C-V) curves of Silicon Metal-Oxide-Semiconductor Capacitors,showing electron and hole trapping at shallow-level dopant and deep-level generation-recombination -trapping impurities,are presented to illustrate the enhancement of the giant trapping capacitances by physical means via device and circuit designs,in contrast to chemical means via impurity characteristics previously reported.Enhancement is realized by masking the electron or/and hole storage capacitances to make the trapping capacitances dominant at the terminals.Device and materials properties used in the computed CV curves are selected to illustrate experimental realizations for fundamental trapping parameter characterizations and for electrical and optical signal processing applications.     

Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method

A two-dimensional quantum mechanical model is presented for calculating carrier transport in ultra-thin gate-all-around quantum wire transistor (GAAQWT) and carbon nanotube field effect transistor (CNTFET) using coupled mode space approach. Schrödinger and Poisson’s equations are self-consistently solved involving Non-Equilibrium Green’s Function (NEGF) formalism under the ballistic limit along with dissipative effects in terms of self-energy at both the source and drain ends. Effect of structural parameters on drain current, channel length modulation parameter, quantum capacitance, transconductance, subthreshold swing (SS) and drain induced barrier lowering (DIBL) are studied assuming occupancy of only a few lower sub-bands, where comparison is performed taking all other factors, biases and dimensions identical. High-k dielectric (HfO₂) independently surrounding the quantum wire (GaAs) and carbon nanotube shows higher drain current and transconductance for GAAQWT but lower quantum capacitance than that obtained for CNTFET. A smaller variation of CLM for CNFET speaks in favour of it for digital quantum circuit applications, whereas GAAQWT is suitable candidate for low-power applications. Effect of structural parameters is investigated within fabrication limit to analyse the effect on electrical characteristics under lower biasing ranges.     

铜线键合优势和工艺的优化

半导体封装对于芯片来说是必须的,也是至关重要的.封装可以指安装半导体集成电路芯片用的外壳,它不仅起着保护芯片和增强导热性能的作用,而且还起到沟通芯片内部世界与外部电路桥梁和规格通用功能的作用.文章阐述了铜线键合替代金线的优势,包括更低的成本、更低的电阻率、更慢的金属问渗透.再通过铜线的挑战--易氧化、铜线硬度大等,提出...     

带负载导线的电磁脉冲响应数值方法研究

现有的细导线算法[1,2,3]只能处理导线两端开路情形,在其基础上提出了一种修正的方法,该方法可以用来计算细导线两端带有负载时电磁脉冲对导线的响应,负载包括电容和电感.在该方法中,导线被分成理想导线、负载和地三个部分,分别用不同的偏微分方程描述,并得到可直接进行计算的差分方程.使用该方法给出了一计算实例,并对计算的结果进行了分析.     

不同结构部件的等效电容对ECM灵敏度的影响

对于驻极体电容传声器(ECM),不同结构部件的等效电容,对灵敏度的影响不同.在掌握了不同类别电容对灵敏废的影响机理之后,在单体设计时,对不同部件进行针对性的设计,以便按需调节单体的灵敏度.主要探讨了振膜的有效电客和传声器内部的寄生电容这两者对灵敏度的影响,以及各部件对相应电容的影响.     

印制板中地线正确连接原则的讨论

印制板的接地方式非常重要,如果地线布线不合理,就可能引起不可接受的测量误差。本文通过一个典型的热电偶数字测温系统的地线连接的分析,来说明PCB中地线正确连接的重要性和接地原则。文章说明了在模拟和数字信号混合系统中连接PCB地线时,应该防止有较大的地电流,特别是应防止数字电路中大的脉冲地电流流入模拟电路的地线中,尤其不应流入小信号模拟电路的地线中。     

Even Order Harmonic Series-L/Parallel-Tuned Class-E Frequency Multiplier

In this brief, we propose a new class-E frequency multiplier based on the recently introduced series-L/parallel-tuned class-E amplifier. The proposed circuit produces even-order output harmonics. Unlike previously reported solutions the proposed circuit can operate under 50% duty ratio which minimizes the conduction losses. The circuit also offers the possibility for increased maximum operating frequency, reduced peak switch voltage, higher load resistance and inherent bond wire absorption; all potentially useful in monolithic microwave integrated circuit implementations. In addition, the circuit topology suggested large transistors with high output capacitances can be deployed. Theoretical design equations are given and the predictions made using these are shown to agree with harmonic balance circuit simulation results.     

一种分析异向介质中导线阵列宏观效应的新方法

本文根据异向介质中细导线阵列的电磁效应,利用均匀介质与均匀传输线的等效关系,建立起电磁波在导线阵列中传播时的等效电路,以此为依据从宏观上推导出异向介质中非均匀导线阵列的有效介电常数模型,在呈现出非常清晰的物理图景的同时,为人们从宏观物理学的角度理解导线阵列的等效负介电常数效应、从实质上揭示异向介质的构成理论向前跨进了一步.数值仿真结果表明,该模型具有足够的精度.本文所得到的结论对理解异向介质的构成提供了更加清晰的描述方法,为异向介质在微波电路领域的应用提供了一套分析方法.     

MOS Capacitance-Voltage Characteristics:Ⅳ.Trapping Capacitance from 3-Charge-State Impurities

正Metal-Oxide-Semiconductor Capacitance-Voltage(MOSCV) characteristics containing giant carrier trapping capacitances from 3-charge-state or 2-energy-level impurities are presented for not-doped,n-doped,pdoped and compensated silicon containing the double-donor sulfur and iron,the double-acceptor zinc,and the amphoteric or one-donor and one-acceptor gold and silver impurities.These impurities provide giant trapping capacitances at trapping energies from 200 to 800 meV(50 to 200 THz and 6 to 1.5μm),which suggest potential sub-millimeter,far-infrared and spin electronics applications.     

可编程SAW滤波器CMOS集成电路的研究

本文介绍了一种采用1 μm CMOS工艺实现的可编程声表面波滤波器的八位取样、加权、控制、叠加集成电路,并对电路的性能进行了模拟和测试,同时与延迟线型、多组IDT型的声表面波滤波器以多芯片模式进行在线功能测试.该电路由两个三明治电容和两个高宽长比的高跨导NMOS晶体管组成.该电路结构简单,制造工艺与传统的CMOS工艺兼容.该集成电路的工作频率范围为15MHz~250MHz时,插入损耗为-8dB~-20dB,加权电路开关比(on/off ratio)为7dB~18dB左右.