On-chip testing of random access memories

This article gives an overview of the Built-In Self-Test techniques for stand alone Random-Access Memory chips. It identifies the limitations of the existing fault models and the test algorithms used to test large RAMs. Methods to reduce test time for testing large RAMs are categorized. The article argues that even linear time test algorithms must use architecture and design for testability induced parallelisms to keep the total test time to an acceptable limit. Following that two algorithms are presented that can be used to test large RAMs for neighborhood pattern sensitive faults. Test lengths and test time for application of these algorithms are computed and it is suggested that a microprogrammed controller based scheme be used to implement self-test in stand alone RAMs.Part of this work was completed when the author was a Visting Professor at the University of Roorkee, India.     

Transparent random access memory testing for pattern sensitive faults

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.This work was supported by the NSF under Grant MIP9208487 and NATO under Grant 910411.     

On the design of random pattern testable PLA based on weighted random pattern testing

Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.     

An efficient design of embedded memories and their testability analysis using Markov chains

This article presents a design strategy for efficient and comprehensive random testing of embedded random-access memory (RAM) where neither are the address, read/write and data input lines directly controllable nor are the data output lines externally observable. Unlike the conventional approaches, which frequently employ on-chip circuits such as linear feedback shift register (LFSR), data registers and multibit comparator for verifying the response of the memory-under-test (MUT) with the reference signature of a fault-free gold unit, the proposed technique uses an efficient testable design, which helps accelerate test algorithms by a factor of 0.5n, if the RAM is organized into an n×1 array and improve the test reliability by eliminating the LFSR that is known to have aliasing problems. Another serious problem in embedded memory testing by random test patterns is the problem of memory initialization, which has been tackled here by adding word-line flag registers. The paper has made indepth empirical studies of the functional faults such as stuck-at, coupling, and pattern-sensitive by suitably representing these faults by Markov chains and by simulating these chains to derive various test lengths required for detecting these faults. The simulation results conclusively show that, in order to test a IM-bit RAM for detecting the common functional faults, the proposed technique needs only one second as opposed to about an hour needed by the conventional random testing where memory cells are tested sequentially.An abridged version of this article was published in the IEEE International Conference on Wafer-Scale Integration, January 1989. This research was partially supported by the NSF under grant number MIP-9013092 and by ONR under grant number 85-K-0716.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

某型军用测试设备可测试性设计验证

在某型军用测试设备设计的初期就考虑可测试性要求,通过优化系统结构并以方便测试为目的进行系统设计,通过故障树的方法从系统层面对测试设备的可测试性进行分析并验证,可为其它测试设备的研制提供参考.     

Analysis of random multiple access transmission systems

For a very large number of small earth-stations with varying transmission time and light traffic, the random multiple access (RMA) transmission system is capable of providing simultaneous access to earth-stations by associating each station with a unique sequence of code symbols. Each information bit will be transformed into these code symbols, where each symbol is an entry in a discrete time-frequency matrix. In this paper we propose a system model for RMA transmission systems and illustrate the application of RMA code sequences. The analysis of this transmission system, which causes interference to the desired signal, is presented. The performance parameter considered is the signal-to-noise ratio (SNR) at the output of a correlation detector. The analysis shows that the SNR depends on the number of users, the energy per data bit and the design of the time-frequency matrix which determines the total numbers and values of the time-delay units associated with any carrier.     

卫星通信系统两步随机接入技术研究

为了实现卫星通信系统低延迟高可靠接入,研究了两步随机接入技术中的信道设计及接收端检测算法.针对卫星场景提出了一种两步随机接入信道设计方案,对两步随机接入信道中数据部分的信道结构以及前导和数据之间的映射方式进行了设计.针对传统最小均方串行干扰消除(Minimum Mean Squared Error-Successive Interference Cancellation,MMSE-SIC)算法中存在误差传播问题导致解码性能降低的问题,提出了一种多判决排序串行干扰消除(Multi-decision Ordered Successive Interference Cancellation,MD-OSIC)算法,以提升多用户发起接入时数据部分检测的可靠性.仿真结果验证了所设计信道及检测算法在典型卫星通信场景下应用的可行性.     

大时延卫星通信的随机接入分段前导检测

针对卫星通信场景下具有较大用户传输时延的特点,提出了一种随机接入分段前导检测算法.不同于现有随机接入前导检测算法中仅提取前导序列区间对应接收信号的做法,该算法根据发送信号中前导序列与保护间隔对应的时间区间,分两段提取接收信号,从而分别估计传输时延的小数倍与整数倍部分.此外,设计了峰值二次有效性评估机制,有效解决了整数倍...     

Testing of static random access memories by monitoring dynamic power supply current

This article presents a correlation between dynamic power supply current and pattern sensitive faults in SRAMs. It is shown that the dynamic power supply current provides a window for observing the internal switching behavior of the memory cells. Switching of the logic state of a memory cell results in a transient current pulse in the power supply rails. A new current-testable SRAM structure is presented which can be used to isolate normal current transients from those resulting from pattern sensitivity. The new structure differs from traditional SRAM structures only in the way that power is distributed to the cells. The new structure allows for very high coverages of disturb-type pattern sensitivity using a simple algorithm of length 5n where n is the number of cells.     

Performance analysis of a new random access protocol for OCDMA networks

A New random access protocol for OC-DMA networks is proposed in this paper. Employing a new mathematical model, namely the processor-sharing system, steady-state throughput ratio and average delay of OCDMA networks are calculated. The results reveal that our protocol outperforms other existing protocols. Meanwhile, we investigate the performance of OCDMA networks by altering the code parameters, i.e., length and weight, and the maximum number of active users in the system, corresponding results are indeed consistent with the practical situation. In addition, the analysis is simplified compared with the conventional Markov chain model. Thus the processor-sharing system is truly applicable to model OCDMA networks. Supported by National Natural Science Foundation of China (NSFC), No. 60472035.     

卫星物联网混合随机接入技术

在卫星物联网(IoT)场景中,随着终端数量不断增加,频谱资源日益紧张。传统的随机接入技术频谱利用率较低,使得传统随机接入协议不适用于未来卫星IoT的高并发业务需求。同时,卫星通信链路长,开放性强,难以保证特种终端信号的安全性。对此,本文提出一种适用于卫星IoT的混合随机接入方案。该方案引入重叠传输的容量提升与安全性优势,利用扩频码对瞬时功率谱密度的控制能力,构造功率域非正交接入条件,并通过接收端的迭代分离实现稳健接收。对本文所提方案的吞吐量性能进行闭式解推导分析与计算机仿真,结果表明,与传统的随机接入协议相比,所提方案可提高系统吞吐量。同时,相较于常用信号隐藏方法,所提方法利用常规接入数据包的功率优势,强化了波形隐藏效果,提升了特种信息接入的安全性。     

铅基卤素钙钛矿阻变式存储器研究进展

随着数字通信在大数据以及物联网等领域的应用,推动了下一代存储设备的发展.阻变式存储器因其功耗低、尺寸可调、操作速度快等优点被认为是最有前景的信息存储器件之一.近年来,兼具成本低、带隙可调、载流子扩散长度长、离子迁移速率快、载流子迁移率高等优点的铅基卤素钙钛矿,在阻变式存储器领域引起了广泛关注.主要对铅基卤素钙钛矿阻变式...     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

A novel magnetic random access memory design using square ring elements for the hard layer

The behavior of narrow permalloy square rings under the influence of a magnetic field was studied using magnetic force microscopy (MFM). Two stable states of opposite polarity at remanence and simple switching were observed. We propose a design for the hard layer of magnetic random access memory (MRAM) that uses these states in square rings for data storage.     

The study of lithographic variation in resistive random access memory

Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (~30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4×, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.     

The effects of power control on the optical CDMA random access protocol

In this work, the performance of the hybrid system that combines the distributed power control algorithm (DPCA) with the random access protocol as a novel and simple scheme of achieving a high performance in decentralized optical code division multiple access (OCDMA) networks has been investigated. The multiple access interference (MAI) and the near-far problem effects have been considered. The DPCA’s advantage lies in its characteristics being effectively implemented to each node, since only local parameters are necessary. The principal results have shown that the network throughput and delay are strongly affected by the near-far problem and the DPCA works to solve this problem. Hence, the introduction of a certain level of the power control to the random access temporally coded (1D) or the time-wavelength coded (2D) OCDMA networks has demonstrated profitability of the throughput increase and the delay reduction. As a consequence, the proposed system configuration with the DPCA using a very low number of iterations has resulted in a better throughput and simultaneously in a delay decrease when compared to the system without power control mechanisms.     

低轨LTE卫星随机接入前导设计及检测算法研究

针对低轨卫星环境中的较广波束覆盖范围和较大多普勒频移的特点,研究了能够应用于低轨LTE（Long Term Evolution）卫星移动通信中的随机接入前导及其检测算法。首先,提出多根长序列（MRLS）,该序列通过级联多个根序列号不同的短ZC（Zadoff-Chu）根序列构建,可以支持一步定时提前估计;其次,提出一种基于MRLS的随机接入前导检测算法,该算法通过相邻短ZC根序列的共轭相乘产生多个检测序列,再与多个待检序列进行联合差分相关检测,克服了整数倍和小数倍子载波间隔的多普勒频移的影响。仿真结果表明,利用MRLS序列,所提算法对载波频率偏移具有很好的鲁棒性,适用于基于LTE的低轨卫星移动通信系统。     

基于GMR及TMR效应的磁随机存储器的最新应用开发

介绍了巨磁电阻（GMR）及隧道磁电阻（TMR）效应,讨论了计算机磁随机存储器（MRAM）的最新应用开发。