基于FPGA和NAND Flash的存储器ECC设计与实现

针对以NAND Flash为存储介质的高速大容量固态存储器,在存储功能实现的过程中可能出现的错“位”现象,在存储器的核心控制芯片,即Xilinx公司Virtex-4系列FPGA XC4VLX80中,设计和实现了用于对存储数据进行纠错的ECC算法模块。在数据存入和读出过程中,分别对其进行ECC编码,通过对两次生成的校验码比较,对发生错误的数据位进行定位和纠正,纠错能力为1 bit/4 kB。ECC算法具有纠错能力强、占用资源少、运行速度快等优点。该设计已应用于某星载存储系统中,为存储系统的可靠性提供了保证。     

一种纠错32位BCH码的硬件实现

针对NANDFlash因制造工艺不断提高而导致其内部数据区随机错误不断增加的现象,传统的8bit,16bit BCH编译码器已难以满足广大客户的需求,现提出了一种新型BCH编译码器结构,所设计的(8640,8192)编码译码器可以在单页数据(1024B)的基础上纠错32bit数据,并在译码电路中,在编码输入电路,伴随式模块与chien搜索模块采取并行算法处理,大大提高了数据的处理速度。     

具有64位数据检纠错功能的FPGA模块设计

星载计算机系统中电子器件容易受到空间环境电磁场的辐射和重粒子的冲击,从而导致器件运行出错,特别是存储器中数据容易出现错误,需要具有检纠错功能的电路模块对其进行纠正,以免造成严重的后果.基于汉明码的纠错原理,根据对64位数据进行检纠错处理的需要,设计一个利用8位校验码,以实现该功能的算法逻辑,并通过FPGA实现.经过仿真验证,该模块具备检测2位错误,纠正1位错误的功能,而且也能较好地满足实时性的要求,具有一定的实际应用意义.     

小容量相变存储器芯片版图设计与验证分析

设计了基于1T1R结构的16 kb相变存储器(PCRAM)芯片及其版图。芯片包括存储阵列、外围读写控制电路、纠错电路(ECC)、静电防护电路(ESD)。版图上对纳米存储单元(1R)与CMOS工艺的融合作了优化处理,给出了提高存储单元操作电流热效率的具体方法。1R位于顶层金属(TM)和二层金属(TM-1)之间,包含存储材料以及上下电极,需要在传统CMOS工艺基础上添加掩膜版。读出放大器采用全对称的差分拓扑结构,大大提升了抗干扰能力、灵敏精度以及读出速度。针对模块布局、电源分配、二级效应等问题,给出了版图解决方案。采用中芯国际130 nm CMOS工艺流片,测试结果显示芯片成品率(bit yield)可达99.7%。     

基于海明编码的EEPROM数据存取功能的实现

针对工业现场对大容量数据存储空间及数据高可靠性的要求,基于单片机的IIC接口,设计了硬件电路和软件读写程序,实现了利用8片24LC512扩展单片机外部EEPROM存储空间的目的.并结合海明码的纠错能力,对数据先编码存储、后解码读取以提高数据的可靠性.现场应用验证,此设计可以实现4 Mbit空间数据的存取,数据准确可靠.     

HDMI2.0接口FEC纠错模块设计

针对HDMI2.0中继器在传输数据的过程中数据因干扰会发生错误的问题,提出了采用前向纠错技术(FEC)来纠正控制周期数据错误而导致的错误视频和音频数据的方案,给出了FEC和HDMI2.0协议相结合的具体过程,实现了基于HDMI2.0接口的数据纠错模块的设计.在Cadence平台下,编写了可综合的Verilog代码实现了电路的设计,并用科学的测试方法对数据纠错模块进行了测试验证.验证结果表明:数据纠错模块和HDMI2.0接口有机地结合在一起,有效纠正了HDMI2.0中继器在数据传输过程中产生的错误,增强了数据传输的可靠性并提高了视听效果.     

高码速率遥感卫星LDPC译码模块设计

随着遥感技术的飞速发展,遥感数据的传输速率和编码性能要求越来越高。在高码速率、复杂编码的条件下,设计符合国际空间数据系统咨询委员会(CCSDS)标准的高码速率解调器成为解决遥感卫星数据解调的关键。在软件无线电平台的解调器结构下,分析低密度奇偶校验码(LDPC)译码特点,完成译码模块结构、解调速率、存储规则的设计。设计结果满足高码速率遥感卫星解调器要求,提高了数据的下传效率和空间资源的利用效率。     

多功能电子药箱的设计与实现

基于药物治疗在临床治疗中的重要性,分析目前服药提醒装置存在的不足,以STM32F103VET6单片机为控制核心,设计了一种多功能电子药箱。该系统包括显示模块、语音模块和数据存储模块。显示模块通过触摸屏电路和LED指示灯电路,与语音模块相配合,实现了服药提醒及指导的功能;数据存储模块通过EEPROM存储电路,能够实现掉电时服药信息不丢失的功能。并且为了实现电子药箱的智能化控制,开发了手机APP,两者之间可通过WIFI进行数据通信。经测试,该药箱能够有效地帮助慢性病患者按时、定量、正确服用药物,适合在家庭中推广使用,具有较高的应用价值和实践意义。     

适于空间图像闪存阵列的非与闪存控制器

提出一种适于空间应用的非与(NAND,not and)闪存控制器。首先,分析了空间相机存储图像的要求,说明了闪存控制器结构的特点。接着,分析了闪存数据存储差错的机理,针对闪存结构组织特点提出了一种基于BCH(Bose-Chaudhuri-Hocquenghem,2108,2048,5)码的闪存纠错算法。然后,对传统BCH编码器进行了改进,提出了一种8bit并行蝶形阵列处理机制。最后,使用地面检测设备对闪存控制器进行了试验验证。结果表明,闪存控制器能快速稳定、可靠地工作,在闪存单页2Kbt/page下可以纠正40bit错误,在相机正常工作行频为2.5kHz下拍摄图像时4级流水线闪存连续写入速度达到133Mbit/s,可以满足空间相机图像存储系统的应用。     

高速低误码高可靠回收存储器设计

本文针对航天飞行器对大容量、高速率以及高冲击环境下可靠回收的要求,提出了一种适用于高速大容量数据存储的设计方法。采用SoftLVDS的高速传输技术、基于ECC纠错编码算法的NAND Flash控制技术以及交叉冗余备份等关键技术,实现了2.4Gbps的高速传输速率,128G字节的大存储容量以及低于10^-10的误码率,同时能够在高冲击环境下实现可靠回收。该产品经过了炮击试验验证,100%获取了试验数据。     

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7×8 μm² and the chip size is 5.55×7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC     

A 50-ns CMOS 256 K EEPROM

A 32 K×8 EEPROM (electrically erasable programmable read-only memory), which operates with a single 5-V power supply and achieves 100 K cycle endurance, 50-ns typical read access time, and 1-ms page programming time, equivalent to 16 μs/byte, was designed. A double-poly, double-metal, n-well CMOS process with 1.25-μm minimum feature size was developed to manufacture the device. The required and optional extended JEDEC standards for software data protection and chip clear are implemented along with parity check, toggle bit, page-load timer, and data-protection status bit. A modified Hamming code, which uses four parity bits per byte, was implemented to detect and correct single-bit errors     

A long lifetime, low error rate RRAM design with self-repair module

Resistive random access memory (RRAM) is one of the promising candidates for future universal memory. However, it suffers from serious error rate and endurance problems. Therefore, exploring a technical solution is greatly demanded to enhance endurance and reduce error rate. In this paper, we propose a reliable RRAM architecture that includes two reliability modules: error correction code (ECC) and self-repair modules. The ECC module is used to detect errors and decrease error rate. The self-repair module, which is proposed for the first time for RRAM, can get the information of error bits and repair wear-out cells by a repair voltage. Simulation results show that the proposed architecture can achieve lowest error rate and longest lifetime compared to previous reliable designs.     

The Design of a High-Performance Error-Correcting Coding Scheme for the Canadian Broadcast Telidon System Based on Reed-Solomon Codes

Error correction can greatly improve the performance and extend the range of broadcast teletext systems. In this paper, the requirements for an error-correcting scheme for broadcast teletext in North America (NABTS) are set down. An error-correction scheme which meets all these requirements is then described. The simplest case employs the one parity bit in each 8 bit byte and no suffix of parity check bits at the end of each data block. The next level also uses a single byte of parity check bits at the end of each data block. Adding a second byte of parity checks at the end of each data block results in a Reed-Solomon code, called theCcode, for each data block. Adding one data block of parity checks afterh - 1data blocks results in a set ofhdata packets being encoded into a bundle, in which verticalCcodes provide powerful interleaving. In a final alternative, two data blocks hold the check bytes for the vertical codewords, and the most powerful coding scheme, the double bundle code, results. The detailed mathematical definitions of the various codes are referred to or described, formulas for performance calculations are referred to, and performance curves are presented for the AWGN channel as well as for measured field data. These performance curves are discussed and compared to the performance of a difference set cyclic code, originally designed for the Japanese teletext system, which corrects any 8 bits in error in a packet.     

一种基于编码的存储器加固设计

在太空辐射环境中存在各种宇宙射线和一些高能粒子,其中单粒子翻转（SEU）效应是引起存储器软错误的重要因素,降低了数据传输的可靠性,因此成为当前集成电路抗辐射加固设计的研究重点之一。标准的纠错编码（ECC）设计冗余度将占用超过50%的存储量,该设计基于缩短汉明码的原理实现了对32位存储器采用7位冗余码进行纠错编码的SEC-DED加固设计,在资源上得到了优化;同时从概率的角度分析了可靠性的理论基础,通过编码可靠性可以提高3到6个数量级。     

Constant amplitude multi-code CDMA with built-in single parity check product code

We show that a constant amplitude multi-code (CAMC) CDMA in a recursive structure can be reconfigured into a single parity check, product code (SPCPC). CAMC can benefit from error correction by parity decoding. We present an algorithm which reconfigures CAMC into an SPCPC structure and then refines the log likelihood ratio of the received bits in an iterative way. Computer simulation results show that CAMC has a superior performance of error correction than a generic SPCPC. Hence, CAMC provides both a low PAPR and robustness to bit errors.     

岸船卫星双向对时应用系统IRIG-B码设计

介绍了现行标准时间码IRIG-B码的编码方式,为满足岸船对时应用系统设计要求,提高岸船时间比对精度,对现行标准时间码IRIG-B码信息格式约定进行了重新设计,使新的IRIG-B码不仅携带时间信息,同时携带测量误差信息、位置信息、控制信息,并在信息位中加入检验位。考虑卫星信道的误码特性,利用空余码位进行纠错编码。仿真结果表明,在不增加卫星传输带宽的前提下,BCH编码可提高传输可靠性。     

Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.     

Designing fault-secure parallel encoders for systematic linear error correcting codes

We consider the open problem of designing fault-secure parallel encoders for various systematic linear ECC. The main idea relies on generating not only the check bits for error correction but also, separately and in parallel, the check bits for error detection. Then, the latter are compared against error detecting check bits which are regenerated from the error correcting check bits. The detailed design is presented for encoders for CRC codes. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that their fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation. Future research will include the design of FS decoders for CRC codes as well as the generalization of the presented ideas to design of FS encoders and decoders for other systematic linear ECC like nonbinary BCH codes and Reed-Solomon codes.     

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

This paper presents a high level error detection and correction method called HVD code to tolerate multiple bit upsets (MBUs) occurred in memory cells. The proposed method uses parity codes in four directions in a data part to assure the reliability of memories. The proposed method is very powerful in error detection while its error correction coverage is also acceptable considering its low computing latency. HVD code is useful for applications whose high error detection coverage is very important such as memory systems. Of course, this code can be used in combination with other protection codes which have high correction coverage and low detection coverage. The proposed method is evaluated using more than one billion multiple fault injection experiments. Multiple bit flips were randomly injected in different segments of a memory system and the fault detection and correction coverages are calculated. Results show that 100% of the injected faults can be detected. We proved that, this method can correct up to three bit upsets. Some hardware implementation issues are investigated to show tradeoffs between different implementation parameters of HVD method.