Power efficient Ka-band low phase noise VCO in 0.13 μm CMOS

A 27 GHz cross-coupled LC voltage controlled oscillator (VCO) using a standard 0.13 mum CMOS technology is presented. The VCO using a high-Q LC resonator with a micro-strip inductor (mu-strip L) provides a phase noise of -113 dBc/Hz at a 1 MHz offset frequency. The figure - of-merit (FoM) is -194.6 dBc/Hz. To obtain high output power, it also uses a common source amplifier as a buffer and it shows the output power of -3.5 dBm at an oscillation frequency of 26.89 GHz. This is believed to be the lowest phase noise and FoM with the highest output power of a millimetre-wave VCO in CMOS technology.     

Noise property of a quadrature balanced VCO

A quadrature balanced voltage controlled oscillator (B-VCO) with current source switching is proposed and analyzed. This letter shows analytically that the switching improves the phase noise. A switched transistor is also used as a coupling transistor to generate quadrature signals without degrading the phase noise. To investigate the effect of quadrature coupling on the phase noise, a single B-VCO and a quadrature B-VCO are implemented with identical components in an 0.18-/spl mu/m CMOS process. Both VCO cores draw about 8.8mA under a low bias voltage of 1.8V. The oscillation frequencies are 10.21GHz and 10.81GHz. The measured phase noises of the single at an offset frequency of 1MHz VCO is -114.83 dBc/Hz while that of the quadrature VCO is -116.67 dBc/Hz. The quadrature B-VCO is superior to the single B-VCO with respect to phase noise and oscillation frequency in the X-band.     

A fully integrated 5.8 GHz U-NII band 0.18-/spl mu/m CMOS VCO

A fully integrated 5.8 GHz CMOS L-C tank voltage-controlled oscillator (VCO) using a 0.18-/spl mu/m 1P6M standard CMOS process for 5 GHz U-NII band WLAN application is presented. The VCO core circuit uses only PMOS to pursue a better phase noise performance since it has less 1/f noise than NMOS. The measurement is performed by using a FR-4 PCB test fixture. The output frequency of the VCO is from 5860 to 6026 MHz with a 166 MHz tuning range and the phase noise is -96.9 dBc/Hz at 300 kHz (or -110 dBc/Hz at 1 MHz) with V ctrl = 0 V. The power consumption of the VCO excluding buffer amplifiers is 8.1 mW at V/sub DD/ = 1.8 V and the output power is -4 dBm.     

A low-noise, 900-MHz VCO in 0.6-μm CMOS

This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-μm CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset     

粗调和细调相结合的标准CMOS低噪声环形压控振荡器

本文提出了一种基于65nm CMOS标准工艺、采用粗调和细调相结合的低噪声环形压控振荡器。论文分析了环形振荡器中的直接频率调制机理,并采用开关电容阵列来减小环形压控振荡器的增益从而抑制直接频率调制效应。开关电容采用电容密度较高的二维叠层MOM电容使该压控振荡器与标准的CMOS工艺兼容。所设计压控振荡器的频率范围为480MHz～1100MHz,调谐范围为78%,测试得到输出频率为495MHz时的相位噪声为-120dBc/Hz@1MHz。该压控振荡器在1.2V的偏压下的功耗为3.84mW,相应的优值(FOM)为-169dBc/Hz。     

一个8GHz高功率AlGaN/GaN HEMT VCO

基于中科院微电子所的AlGaN/GaN HEMT工艺研制了一个X波段高功率混合集成压控振荡器（VCO）。电路采用源端调谐的负阻型结构,主谐振腔由开路微带和短路微带并联构成,实现高Q值设计。在偏置条件为VD=20V, VG=-1.9V, ID=150mA时,VCO在中心频率8.15 GHz处输出功率达到28 dBm,效率21%,相位噪声-85 dBc/Hz@100 KHz,-128 dBc/Hz@1 MHz。调谐电压0~5V时,调谐范围50 MHz。分析了器件闪烁噪声对GaN HEMT基振荡器相位噪声性能的主导作用。测试结果显示了AlGaN/GaN HEMT工艺在高功率低噪声微波频率源中的应用前景。     

A Differentially-Tuned Voltage ControlledOscillator Using Symmetric Transformer

This letter proposes a new voltage controlled oscillator (VCO) topology that cancels common-mode noise by adoption of differential tuning varactor. To suppress common mode noise effectively, a symmetric three-coil transformer is proposed as a differential tuning resonator. The measured phase noise shows -128.7 dBc/Hz at 1 MHz offset frequency from the 1.2 GHz oscillation frequency. Over the whole frequency range, common-mode noise rejection is larger than 36 dB. Measured tuning range of the proposed VCO is about 204 MHz from the 1.18 GHz to 1.38 GHz while dissipating 1.2 mA at 1.8 V power supply.     

A single-chip Si-bipolar 1.6-GHz VCO with integrated-bias network

A single-chip 2.7-V voltage-controlled oscillator (VCO) with an integrated-bias network has been implemented in an Si-bipolar process with an f_T of 25 GHz. With an on-chip resonator consisting of vertically coupled inductors and varactor diodes, an oscillation frequency of 1.56 GHz was measured. A careful design of the oscillator and bias network was necessary to achieve a phase noise performance of -139 dBc/Hz at 4.7 h MHz off carrier. The tuning sensitivity was 100 MHz/V, which is sufficient to compensate for production tolerances. The VCO can be used as a building block for single-chip transceivers in digital European cordless telephone or global system for mobile communication systems     

An Amplitude-Balanced Current-Reused CMOS VCO Using Spontaneous Transconductance Match Technique

A 3.5 GHz, 0.18 $mu{rm m}$ CMOS current-reused voltage-controlled oscillator (VCO) with very high amplitude balance is presented. While the current-reused VCO can dramatically save dc power consumption, it has the drawback of output amplitude imbalance resulting from the asymmetric circuit structure. A spontaneous transconductance match (STM) technique is proposed to balance the transconductance of nMOS and pMOS transistors by the imbalance-induced voltage at the center-tapped point of the tank inductor. This transconductance match takes place spontaneously with the occurrence of signal imbalance such that imbalances can be instantly eliminated. The measured amplitude imbalance ratio is less than 0.7% over the entire tuning range of 2.93 to 3.62 GHz, significantly reduced from 3% of the VCO without STM. The power consumption is as low as 1.65 mW from a 1.5 V supply. The phase noise is $-$ 122 dBc/Hz at 1 MHz offset. A very high FOM of $-$195.7 dBc/Hz is achieved.      

A 5 GHz, 192.6 dBc/Hz/mW FOM, LC–VCO System With Amplitude Control Loop and LDO Voltage Regulator in 0.18 μm CMOS

To reduce phase noise degradation from oscillator tail current sources, this letter presents an inductor-capacitor voltage-controlled oscillator (LC-VCO) biased by triode metal-oxide-semiconductor transistors. The VCO system also includes an amplitude control loop and a voltage regulator to endure process, voltage, and temperature variations and to enhance power supply rejection ratio. Fabricated in a 0.18 mum CMOS process, the measured results show the adopted topology achieves a better phase noise than the conventional saturation current source. At 5.181 GHz, the VCO system demonstrates a phase noise of -104.8 dBc/Hz at 100-kHz offset, and -127.1 dBc/Hz at 1 MHz offset, while dissipating 4.2 mA from a 1.8 V supply voltage. The corresponding figures of merit at 100 kHz and 1 MHz offset are 190.3 and 192.6 dBc/Hz/mW, respectively.     

射频卫星电视天线电路中LC压控振荡器设计

本文设计了一款应用于卫星电视天线电路中低功耗、低相噪的宽带单片集成压控振荡器。该振荡器利用PMOS尾电流源和MIM电容阵列结构。在保证调谐范围的前提下,有效的降低了相位噪声。使得该压控振荡器实现了3.384GHz~4.022GHz频段的覆盖,在中心频率为3.7GHz时,100Hz和1MHz频偏处的相位噪声分别为-90.4dBc/Hz和-119.1dBc/Hz,工作电压下为1.8V,功耗仅为2.5mW。     

A low-noise voltage-controlled ring oscillator in 28-nm FDSOI technology for UWB applications

In millimeter wave systems, performance degradation mainly occurs due to high phase noise of voltage-controlled oscillators (VCOs). This paper proposes a low power, low phase noise ring-VCO developed for ultra-wide band applications identified for possible 5G usage. For this purpose, a novel differential symmetrical load delay cell based 3-stage ring oscillator has been introduced to design the ring-VCO. The 28 nm CMOS Fully Depleted Silicon On Insulator (FDSOI) technology is adopted for designing this VCO circuit with 1 V power supply while a new voltage control through the transistor body bias is implemented. The simulated results show that the proposed oscillator works in the tuning range of 29–49 GHz and dissipates 3.75 mW of power. It exhibits a phase noise of −129.2 dBc/Hz at 1 MHz offset from 49 GHz oscillation frequency, and a remarkable Figure of Merit (FoM) of −217.26 dBc/Hz. With similar power supply, the phase noise rises to −93.16 dBc/Hz for a second oscillator involving more of active components exactly 9 delay cells. Further, the impact of the operation temperature variation on the VCO performance is investigated. Results show a drift in the oscillation frequency for a temperature step from 27 °C to 40 °C and a degradation of 3dBc in the phase noise performance.     

一个6GHz宽带低相位噪声CMOS LC VCO

用SMIC 0.13 μm CMOS工艺实现了一个低相位噪声的6 GHz压控振荡器(VCO).在对其相位噪声分析的基础上,通过改进和优化传统的调谐单元和噪声滤波电路以及加入源极负反馈电阻实现了一个宽带、低增益、低相位噪声VCO.测试结果显示,在中心频率频偏1 MHz处的相位噪声为-119 dBc/Hz,频率调谐范围为6...     

用于434/868MHz FSK/OOK CMOS发射机的锁相环设计

一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。     

A 15/30-GHz Dual-Band Multiphase Voltage-Controlled Oscillator in 0.18- μm CMOS

A multiphase oscillator suitable for 15/30-GHz dual-band applications is presented. In the circuit implementation, the 15-GHz half-quadrature voltage-controlled oscillator (VCO) is realized by a rotary traveling-wave oscillator, while frequency doublers are adopted to generate the quadrature output signals at the 30-GHz frequency band. The proposed circuit is fabricated in a standard 0.18-mum CMOS process with a chip area of 1.1times1.0 mm². Operated at a 2-V supply voltage, the VCO core consumes a dc power of 52 mW. With a frequency tuning range of 250 MHz, the 15-GHz half-quadrature VCO exhibits an output power of -8 dBm and a phase noise of -112 dBc/Hz at 1-MHz offset frequency. The measured power level and phase noise of the 30-GHz quadrature outputs are -16 dBm and -104 dBc/Hz, respectively     

A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT

A 6 GHz voltage controlled oscillator (VCO) optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance (Neg-R) method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of -122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.     

A 5-GHz fully integrated full PMOS low-phase-noise LC VCO

A 5-GHz fully integrated, full PMOS, low-phase-noise and low-power differential voltage-controlled oscillator (VCO) is presented. This circuit is implemented in a 0.35-/spl mu/m four-metal BiCMOS SiGe process. At 2.7-V power supply voltage and a total power dissipation of only 13.5 mW, the proposed VCO features a worst case phase noise of -97 dBc/Hz and -117 dBc/Hz at 100 kHz and 1 MHz frequency offset, respectively. The oscillator is tuned from 5.13 to 5.68 GHz with a tuning voltage varying from 0 to 2.7 V.     

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.     

5-GHz Low Phase-Noise CMOS VCO Integrated With a Micromachined Switchable Differential Inductor

A 5-GHz CMOS voltage-controlled oscillator (VCO) integrated with a micromachined switchable differential inductor is reported in a 0.18 mum radio frequency-CMOS-based microelectromechanical system technology. The power consumption of the core is about 8 mW at the supply voltage of 1.8 V. A total tuning range of 470 MHz (from 5.13 GHz to 5.60 GHz) is achieved as the tuning voltage ranging from 0 V to 1.8 V. In the practical tuning range, the measured phase noise performances at 1 MHz offset are less than -125 dBc/Hz and -126 dBc/Hz when the inductor switch is turned on and off, respectively. The figure-of-merit is better than -190 dB. When compared with a contrast VCO circuit that utilizes a standard switchable differential inductor, this oscillator reaches a phase noise improvement of around 3 dB as the switch is turned on. Around 1-dB on-off phase noise difference can be achievable.     

基于电感电容振荡器的电荷泵锁相环的设计

设计并实现了一种采用电感电容振荡器的电荷泵锁相环,分析了锁相环中鉴频/鉴相器(PFD)、电荷泵(CP)、环路滤波器(LP)、电感电容压控振荡器(VCO)的电路结构和设计考虑。锁相环芯片采用0.13μm MS&RF CMOS工艺制造。测试结果表明,锁相环锁定的频率为5.6～6.9 GHz。在6.25 GHz时,参考杂散为-51.57 dBc;1 MHz频偏处相位噪声为-98.35 dBc/Hz;10 MHz频偏处相位噪声为-120.3 dBc/Hz;在1.2 V/3.3 V电源电压下,锁相环的功耗为51.6 mW。芯片总面积为1.334 mm2。